SPEAR600 datasheet(15/97 Pages) STMICROELECTRONICS

15 / 97 page

SPEAr600

Architecture overview

Doc ID 16259 Rev 3

15/97

2.5

Multichannel DMA controller

Within its basic subsystem, SPEAr600 provides a DMA controller (DMAC) able to service up

to 8 independent DMA channels for serial data transfers between a single source and

destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to-memory, and

peripheral-to-peripheral).

Each DMA channel can support unidirectional transfers, with one internal four-word FIFO

per channel.

2.6

LCD controller

Main features:

●

Resolution programmable up to 1024 x 768

●

16-bpp true-color non-palletized, for color STN and TFT

●

24-bpp true-color non-palletized, for color TFT

●

Supports single and dual panel mono super twisted nematic (STN) displays with 4 or 8-

bit interfaces

●

Supports single and dual-panel color and monochrome STN displays

●

Supports thin film transistor (TFT) color displays

●

15 gray-level mono, 3375 color STN, and 32 K color TFT support

●

1, 2, or 4 bits per pixel (bpp) palletized displays for mono STN

●

1, 2, 4 or 8-bpp palletized color displays for color STN and TFT

●

Programmable timing for different display panels

●

256 entry, 16-bit palette RAM, arranged as a 128 x 32-bit RAM physically frame, line

and pixel clock signals

●

AC bias signal for STN and data enable signal for TFT panels patented gray scale

algorithm

●

Supports little-endian, big-endian and WinCE data formats

2.7

GPIOs

The General Purpose Input/Outputs (GPIOs) provide programmable inputs or outputs.

Each input/output can be controlled in two distinct modes:

●

Software mode, through an APB interface

●

Hardware mode, through a hardware control interface.

SPEAr600 provides up to 10 GPIO lines:

●

Individually programmable input/output pins (default to input at reset)

●

An APB slave acting as control interface in "software mode"

●

Programmable interrupt generation capability on any number of pins

●

Bit masking in both read and write operations through address lines

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