SPEAR600 datasheet(12/97 Pages) STMICROELECTRONICS

12 / 97 page

Architecture overview

SPEAr600

12/97

Doc ID 16259 Rev 3

market. The user custom logic can be configured using the following SoC internal

resources:

●

130 Kbyte of static memory arranged in four 32 KB macro group and one 2 KB group.

●

Up to 17 selectable source clocks (either internal or external)

●

DMA support (up to 16 configurable dma input/output request lines)

●

Power management I/F

●

Interrupts line (12 outputs - 64 inputs)

●

4 AHB output master ports interconnected with the multi-channel memory controller

●

5 AHB input slave ports

●

1 interconnection port with the Expansion Interface bus (EXPI)

●

9 LVDS (8 outputs - 1 input) signals

●

88/112 PL_GPIOs primary input/output signals

Caution:

PL GPIO pins are not configurable by software.

Common Subsystem

This block consists of four different logic subsystems used to control the SoC basic

functions:

●

I/O connectivity:

–

Low speed: UARTs, SSPs, I2C and IrDA

–

High speed: MII 10/100/1000, USB 2.0 host and devices

●

Hardware accelerator: JPEG-codec and DMA

●

Video: Color LCD interface

●

Common resources: Timers, GPIOs, RTC and Watchdog

●

Power management functionality

●

SoC configurability: Miscellaneous control logic

CPU Subsystem

The SPEAr600 has a symmetric processor architecture with:

●

2 equivalent subsystems including the ARM926 and its private subsystem logic

(GPIOs, Interrupt controller and Timer) providing the essential hardware resources to

support a generic Operating System

●

The subsystem is replicated twice so both processors have the same memory map.

This structure enables a true symmetric multi-processor architecture were both

processors can simultaneously execute the same OS (all interrupt sources are handled

by both processors)

●

All internal peripherals are shared, allowing flexible and efficient software partitions.

●

High aggregate throughput can be sustained by splitting critical tasks either onto

additional CPUs and optional hardware accelerator engines.

●

Both processors are equipped with ICE and ETM configurable debug interfaces. for

real-time CPU activity tracing and debugging.

4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode is supported,

with normal or half-rate clock.

The internal architecture is also based on several shared subsystem logic blocks

interconnected through a multilayer interconnection matrix. The switch matrix structure

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