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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPEAR600 датащи(PDF) 8 Page - STMicroelectronics |
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SPEAR600 датащи(HTML) 8 Page - STMicroelectronics |
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8 / 97 page  Description SPEAr600 8/97 Doc ID 16259 Rev 3 1 Description The SPEAr600 is a member of the SPEAr family of embedded MPUs for networked devices, it is based on dual ARM926EJ-S processors (up to 333 MHz), widely used in applications where high computation performance is required. Both processors have an MMU supporting virtual memory management and making the system compliant with the Linux operating system. They also offer 16 KBytes of data cache, 16 KBytes of instruction cache, JTAG and ETM (embedded trace macro-cell) for debug operations. To expand its range of target applications, SPEAr600 can be extended by adding additional peripherals through the external local bus (EXPI interface). Figure 1. Functional block diagram MultiChannel DMA controller LCD controller 1024*768 DDR1/DDR2 memory controller 32 KBytes BootRom 8 KBytes SRAM NAND Flash controller Serial Flash Interface Ethernet Controller 10/100/1000 Mbps JPEG Codec accelerator Watchdog RTC Timers PLLs ARM926EJ-S @333 MHz System controller Interrupt controller ICache DCache MMU ARM926EJ-S @333 MHz System controller Interrupt controller ICache DCache MMU USB Device 2.0 +Phy USB Host 2.0 +Phy USB Host 2.0 +Phy 2x UART I2C master/slave Fast IrDA 3x SSP ADC 10-bit 8ch GPIO 10x Timers 3x I2S EXPI I/f |
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