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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPEAR600 датащи(PDF) 62 Page - STMicroelectronics |
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SPEAR600 датащи(HTML) 62 Page - STMicroelectronics |
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62 / 97 page  Timing characteristics SPEAr600 62/97 Doc ID 16259 Rev 3 Figure 7. DDR2 write cycle path Table 34 shows the internal chip timing without the contribution of the pads. These values are obtained considering the nominal setting of DLL at T period for DQS path and T*3/4 for DQ path, in fact the memory controller launches data (DQ) and data strobe (DQS) misaligned. Internally the clock is delayed by T to produce the DQS and the same clock is delayed by T*3/4 to clock the data DQ, in order to perform a correct write to the memory. The table values are measured in a particular pad configuration: Drive strength = strong (zprog_out = L) Slope : prog_a = L ; prog_b = H (corresponding to 266 MHz) The waveforms in Figure 6 refer to the pad or memory side, so the DQS edges are centered on the data valid window. In this case, we consider the minimum values for t4 and t5 in order to obtain the minimum data valid window. For a correct data write (on the memory side) the last variation of the data must precede the first arrival of the data strobe. In other words, we can consider t4 as the tSETUP of the data that can be defined as the time range where the Table 33. DDR2 write cycle path timings without pad delay t3MAX (t1 + t2)MIN t3MIN (t1 + t2)MAX Rising best 2.19 ns 2.08 ns 1.91 ns 2.13 ns Falling best 2.21 ns 2.11 ns 1.95 ns 2.15 ns Rising worst 5.55 ns 5.28 ns 5.2 ns 5.33 ns Falling worst 5.54 ns 5.30 ns 5.3 ns 5.35 ns Table 34. DDR2 write cycle timings without pad delay Period (T) Frequency t4MIN t5MIN 3 ns 333 MHz 396 ps 492 ps 3.75 ns 266 MHz 585 ps 681 ps 5 ns 200 MHz 895 ps 991 ps 6 ns 166 MHz 1.15 ns 1.25 ns 7.5 ns 133 MHz 1.52 ns 1.62 ns Q Q SET CLR D Q Q SET CLR D t1 t2 DLL2 t3 DQS DQ CLK DLL1 |
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