ST72561AR7-Auto datasheet(321/324 Pages) STMICROELECTRONICS

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ST72561-Auto

Important notes

Doc ID 12370 Rev 8

321/324

Analysis

The LIN protocol specifies a minimum of 13 bits for the break duration, but there is no

maximum value. Nevertheless, the maximum length of the header is specified as

(14 + 10 + 10 + 1) x 1.4 = 49 bits. This is composed of:

●

the synch break field (14 bits)

●

the synch field (10 bits)

●

the identifier field (10 bits)

Every LIN frame starts with a break character. Adding an idle character increases the length

of each header by 10 bits. When the problem occurs, the header length is increased by 11

bits and becomes ((14 + 11) + 10 + 10 + 1) = 45 bits.

To conclude, the problem is not always critical for LIN communication if the software keeps

the time between the sync field and the ID smaller than 4 bits, that is, 208µs at 19200 baud.

The workaround is the same as for SCI mode but considering the low probability of

occurrence (1%), it may be better to keep the break generation sequence as it is.

24.2.2

16-bit and 8-bit timer PWM mode

In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R or

OC2R register.

24.3

ROM devices only

24.3.1

16-bit timer PWM mode buffering feature change

In all devices, the frequency and period of the PWM signal are controlled by comparing the

counter with a 16-bit buffer updated by the OCiHR and OCiLR registers. In ROM devices,

contrary to the description in Pulse width modulation mode, the output compare function is

not inhibited after a write instruction to the OCiHR register. Instead the buffer update at the

end of the PWM period is inhibited until OCiLR is written. This improved buffer handling is

fully compatible with applications written for Flash devices.

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