ST72344S2 datasheet(134/247 Pages) STMICROELECTRONICS

134 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

134/247

Doc ID 12321 Rev 6

Character transmission

During an SCI transmission, data shifts out least significant bit first on the TDO pin. In

this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and

the transmit shift register (see Figure 64).

Procedure:

–

Select the M bit to define the word length.

–

Select the desired baud rate using the SCIBRR and the SCIETPR registers.

–

Set the TE bit to send an idle frame as first transmission.

–

Access the SCISR register and write the data to send in the SCIDR register (this

sequence clears the TDRE bit). Repeat this sequence for each data to be

transmitted.

Clearing the TDRE bit is always performed by the following software sequence:

An access to the SCISR register

A write to the SCIDR register

The TDRE bit is set by hardware and it indicates:

–

The TDR register is empty.

–

The data transfer is beginning.

–

The next data can be written in the SCIDR register without overwriting the

previous data.

This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR

When a transmission is taking place, a write instruction to the SCIDR register stores

the data in the TDR register and which is copied in the shift register at the end of the

current transmission.

When no transmission is taking place, a write instruction to the SCIDR register places

the data directly in the shift register; the data transmission starts, and the TDRE bit is

immediately set.

When a frame transmission is complete (after the stop bit or after the break frame) the

TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the

CCR register.

Clearing the TC bit is performed by the following software sequence:

An access to the SCISR register

A write to the SCIDR register

Note:

The TDRE and TC bits are cleared by the same software sequence.

Break characters

Setting the SBK bit loads the shift register with a break character. The break frame

length depends on the M bit (see Figure 64).

As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing

this bit by software the SCI insert a logic 1 bit at the end of the last break frame to

guarantee the recognition of the start bit of the next frame.

Idle characters

Setting the TE bit drives the SCI to send an idle frame before the first data frame.

Clearing and then setting the TE bit during a transmission sends an idle frame after the

current word.

ST72344S2 датащи(PDF) 134 Page - STMicroelectronics

ST72344S2 датащи(HTML) 134 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL