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ST72344S2 датащи(PDF) 110 Page - STMicroelectronics |
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ST72344S2 датащи(HTML) 110 Page - STMicroelectronics |
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110 / 247 page ![]() On-chip peripherals ST72344xx, ST2345xx 110/247 Doc ID 12321 Rev 6 length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register. Bits 3:2 = CC[1:0] Clock Control. The timer clock mode depends on these bits: Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input Edge 2. This bit determines which type of level transition on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = EXEDG External Clock Edge. This bit determines which type of level transition on the external clock pin EXTCLK will trigger the counter register. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register. Control/status register (CSR) Reset value: 0000 0000 (00h) The three least significant bits are not used. Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Table 50. Clock control bits Timer clock CC1 CC0 fCPU / 4 0 0 fCPU / 2 0 1 fCPU / 8 1 0 External clock (where available) 1 1 7 0 ICF1 OCF1 TOF ICF2 OCF2 TIMD 0 0 Read-only |
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