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ST72344S2 датащи(PDF) 103 Page - STMicroelectronics

номер детали ST72344S2
подробное описание детали  SCI asynchronous serial interface
PDF  247 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
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ST72344S2 датащи(HTML) 103 Page - STMicroelectronics

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ST72344xx, ST2345xx
On-chip peripherals
Doc ID 12321 Rev 6
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One-pulse mode
One-pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one-pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure:
To use one-pulse mode:
1.
Load the OC1R register with the value corresponding to the length of the pulse (see the
formula in the opposite column).
2.
Select the following in the CR1 register:
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
3.
Select the following in the CR2 register:
Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
Set the OPM bit.
Select the timer clock CC[1:0] (see Table 50: Clock control bits).
Figure 52.
One-pulse mode cycle
When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1
register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin
and the ICF1 bit is set.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1.
Reading the SR register while the ICFi bit is set.
2.
An access (read or write) to the ICiLR register.
event occurs
Counter
= OC1R
OCMP1 = OLVL1
When
When
on ICAP1
One-pulse mode cycle
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
ICR1 = Counter



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