ST72344K2 datasheet(171/247 Pages) STMICROELECTRONICS

171 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

171/247

Word mode is disabled by hardware after the word update is performed. It must be

enabled before each word update by CPU.

Use the following procedure when the ST7 writes a word in RAM:

Disable interrupts

Enable Word mode by setting the B/W and BusyW bits in the I2C3SCR2 register.

BusyW bit is set to 1 when modifying any bits in Control Register 2. Writing a 1 to this

bit does not actually modify BusyW but prevents accidental clearing of the bit.

Write Byte 1 in an even address in RAM. The byte is not actually written in RAM but in

a shadow register. This address must be within the I2C RAM buffer of slave addresses

1, 2 or 3.

Write Byte 2 in the next higher address in RAM. This byte is actually written in RAM.

During the next cycle, the shadow register content is written in the lower address. The

DMA request is disabled during this cycle.

Byte mode resumes automatically after writing byte 2 and DMA is re-enabled.

Enable interrupts

Note:

Word mode does not guarantee byte-pair coherency of words WRITTEN by the I2C master

in RAM and read by the ST7. In this case, byte pair coherency must be handled by software.

Figure 73.

16-bit word write operation flowchart

Sends address

and write bit

Decodes I2C3SNS address

decodes R/W bit

sets write flag

Sends write address

Sends 1 byte of data

STOP condition

Updates current address-

Issues DMA request

Resets I2C3SNS write flag

Halts execution

Resumes execution

Services I2C3SNS interrupt

Reads I2C3SNS status register

Delays while CPU

completes word write

Sets BUSYW in control -

Word mode?

HOST

ST7 CPU

ST7 I2C3SNS

Repeat

RAM start address depends on slave address

Byte-Pair Coherency ensured by setting Word Mode

Normal execution

max

1 Cycle

Writes one byte to RAM

max

1 Cycle

issues interrupt

Enables I2C3SNS

Updates control register

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