ST72344K2 datasheet(161/247 Pages) STMICROELECTRONICS

161 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

161/247

Bit 7 = EVF Event flag.

This bit is set by hardware as soon as an event occurs. It is cleared by software reading

SR2 register in case of error event or as described in Figure 69. It is also cleared by

hardware when the interface is disabled (PE=0).

0: No event

1: One of the following events has occurred:

●

BTF=1 (Byte received or transmitted)

●

ADSL=1 (Address matched in Slave mode while ACK=1)

●

SB=1 (Start condition generated in Master mode)

●

AF=1 (No acknowledge received after byte transmission)

●

STOPF=1 (Stop condition detected in Slave mode)

●

ARLO=1 (Arbitration lost in Master mode)

●

BERR=1 (Bus error, misplaced Start or Stop condition detected)

●

ADD10=1 (Master has sent header byte)

●

Address byte successfully transmitted in Master mode.

Bit 6 = ADD10 10-bit addressing in Master mode.

This bit is set by hardware when the master has sent the first byte in 10-bit address

mode. It is cleared by software reading SR2 register followed by a write in the DR

is disabled (PE=0).

0: No ADD10 event occurred.

1: Master has sent first address byte (header)

Bit 5 = TRA Transmitter/Receiver.

When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically

when BTF is cleared. It is also cleared by hardware after detection of Stop condition

(STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0).

0: Data byte received (if BTF=1)

1: Data byte transmitted

Bit 4 = BUSY Bus busy.

This bit is set by hardware on detection of a Start condition and cleared by hardware on

detection of a Stop condition. It indicates a communication in progress on the bus. The

BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.

0: No communication on the bus

1: Communication ongoing on the bus

Bit 3 = BTF Byte transfer finished.

This bit is set by hardware as soon as a byte is correctly received or transmitted with

interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by

a read or write of DR register. It is also cleared by hardware when the interface is

disabled (PE=0).

●

Following a byte transmission, this bit is set after reception of the acknowledge clock

pulse. In case an address byte is sent, this bit is set only after the EV6 event (See

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