ST72344K2 datasheet(127/247 Pages) STMICROELECTRONICS

127 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

127/247

Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read-only)

This bit is set by hardware when a transfer has been completed. An interrupt is

generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an

access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been cleared.

1: Data transfer between the device and an external device has been completed.

Note:

While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR

Bit 6 = WCOL Write collision status (Read-only)

This bit is set by hardware when a write to the SPIDR register is done during a transmit

sequence. It is cleared by a software sequence (see Figure 61).

0: No write collision occurred

1: A write collision has been detected

Bit 5 = OVR SPI overrun error (Read-only)

This bit is set by hardware when the byte currently being received in the shift register is

ready to be transferred into the SPIDR register while SPIF = 1 (See Overrun condition

(OVR)). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is

cleared by software reading the SPICSR register.

0: No overrun error

1: Overrun error detected

Bit 4 = MODF Mode fault flag (Read-only)

This bit is set by hardware when the SS pin is pulled low in master mode (see Master

mode fault (MODF)). An SPI interrupt can be generated if SPIE = 1 in the SPICR

while MODF = 1 followed by a write to the SPICR register).

0: No master mode fault detected

1: A fault in master mode has been detected

Bit 3 = Reserved, must be kept cleared.

Bit 2 = SOD SPI Output disable

This bit is set and cleared by software. When set, it disables the alternate function of

the SPI output (MOSI in master mode / MISO in slave mode)

0: SPI output enabled (if SPE = 1)

1: SPI output disabled

Bit 1 = SSM SS management

This bit is set and cleared by software. When set, it disables the alternate function of

the SPI SS pin and uses the SSI bit value instead. See Slave select management.

0: Hardware management (SS managed by external pin)

1: Software management (internal SS signal controlled by SSI bit. External SS pin free

for general-purpose I/O)

Bit 0 = SSI SS internal mode

This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of

the SS slave select signal when the SSM bit is set.

0: Slave selected

1: Slave deselected

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