ENICSF2811PBKA datasheet(137/172 Pages) TI1

137 / 172 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174T – APRIL 2001 – REVISED MAY 2012

6.27 External Interface Ready-on-Write Timing With One External Wait State

Table 6-39. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)

PARAMETER

MIN

MAX

UNIT

td(XCOH-XZCSL)

Delay time, XCLKOUT high to zone chip-select active-low

td(XCOHL-XZCSH)

Delay time, XCLKOUT high or low to zone chip-select inactive-high

–2

td(XCOH-XA)

Delay time, XCLKOUT high to address valid

td(XCOHL-XWEL)

Delay time, XCLKOUT high/low to XWE low

td(XCOHL-XWEH)

Delay time, XCLKOUT high/low to XWE high

td(XCOH-XRNWL)

Delay time, XCLKOUT high to XR/W low

td(XCOHL-XRNWH)

Delay time, XCLKOUT high/low to XR/W high

–2

ten(XD)XWEL

Enable time, data bus driven from XWE low

td(XWEL-XD)

Delay time, data valid after XWE active-low

th(XA)XZCSH

Hold time, address valid after zone chip-select inactive-high

(1)

th(XD)XWE

Hold time, write data valid after XWE inactive-high

TW – 2(2)

tdis(XD)XRNW

Maximum time for DSP to release the data bus after XR/W inactive-high

(1)

During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.

(2)

TW = trail period, write access. See Table 6-30.

Table 6-40. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1)

MIN

MAX

UNIT

tsu(XRDYsynchL)XCOHL

Setup time, XREADY (synchronous) low before XCLKOUT high/low

th(XRDYsynchL)

Hold time, XREADY (synchronous) low

Earliest time XREADY (synchronous) can go high before the sampling

te(XRDYsynchH)

XCLKOUT edge

tsu(XRDYsynchH)XCOHL

Setup time, XREADY (synchronous) high before XCLKOUT high/low

th(XRDYsynchH)XZCSH

Hold time, XREADY (synchronous) held high after zone chip-select high

(1)

The first XREADY (synchronous) sample occurs with respect to E in Figure 6-35:

E = (XWRLEAD + XWRACTIVE) tc(XTIM)

When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to

be low, it will be sampled again each tc(XTIM) until it is found to be high.

For each sample, setup time from the beginning of the access can be calculated as:

D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL

where n is the sample number (n = 1, 2, 3, and so forth).

Table 6-41. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1)

MIN

MAX

UNIT

tsu(XRDYasynchL)XCOHL

Setup time, XREADY (asynchronous) low before XCLKOUT high/low

th(XRDYasynchL)

Hold time, XREADY (asynchronous) low

Earliest time XREADY (asynchronous) can go high before the sampling

te(XRDYasynchH)

XCLKOUT edge

tsu(XRDYasynchH)XCOHL

Setup time, XREADY (asynchronous) high before XCLKOUT high/low

th(XRDYasynchH)XZCSH

Hold time, XREADY (asynchronous) held high after zone chip-select high

(1)

The first XREADY (synchronous) sample occurs with respect to E in Figure 6-36:

E = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)

When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found

to be low, it will be sampled again each tc(XTIM) until it is found to be high.

For each sample, setup time from the beginning of the access can be calculated as:

D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL

where n is the sample number (n = 1, 2, 3, and so forth).

Electrical Specifications

137

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