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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ENICSF2811PBKA датащи(PDF) 136 Page - Texas Instruments |
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ENICSF2811PBKA датащи(HTML) 136 Page - Texas Instruments |
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136 / 172 page  t su(XD)XRD Lead Active Trail DIN t d(XCOH-XZCSL) t d(XCOH-XA) t d(XCOHL-XRDL) t d(XCOHL-XZCSH) t d(XCOHL-XRDH) WS (Async) XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK XZCS0AND1 XZCS2 XZCS6AND7 , , XA[0:18] XRD XWE XR/W XD[0:15] XREADY(Asynch) t su(XRDYasynchL)XCOHL t a(A) t h(XD)XRD t h(XRDYasynchH)XZCSH See Notes (A) and (B) See Note (C) t su(XRDYasynchH)XCOHL See Note (D) = Don’t care. Signal can be high or low during this time. Legend: t e(XRDYasynchH) See Note (E) t a(XRD) t h(XRDYasynchL) TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 SPRS174T – APRIL 2001 – REVISED MAY 2012 www.ti.com A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals will transition to their inactive state. C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles. D. For each sample, setup time from the beginning of the access can be calculated as: D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYAsynchL)XCOHL where n is the sample number (n = 1, 2, 3, and so forth). E. Reference for the first sample is with respect to this point: E = (XRDLEAD + XRDACTIVE – 2) tc(XTIM) Figure 6-34. Example Read With Asynchronous XREADY Access XTIMING register parameters used for this example: XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE 1 = XREADY ≥ 1 3 ≥ 1 1 0 N/A(1) N/A(1) N/A(1) (Async) (1) N/A = “Don’t care” for this example 136 Electrical Specifications Copyright © 2001–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 |
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