ENICSF2811PBKA datasheet(31/172 Pages) TI1

31 / 172 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174T – APRIL 2001 – REVISED MAY 2012

The XINTF consists of five independent zones. One zone has its own chip select and the remaining four

zones share two chip selects. Each zone can be programmed with its own timing (wait states) and to

either sample or ignore external ready signal. This makes interfacing to external peripherals easy and

glueless.

NOTE

The chip selects of XINTF Zone 0 and Zone 1 are merged into a single chip select

(XZCS0AND1); and the chip selects of XINTF Zone 6 and Zone 7 are merged into a single

chip select (XZCS6AND7). See Section 3.5, External Interface, XINTF (2812 only), for

details.

Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together to enable these blocks

to be “write/read peripheral block protected”. The “protected” mode ensures that all accesses to these

blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to

different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause

problems in certain peripheral applications where the user expected the write to occur first (as written).

The C28x CPU supports a block protection mode where a region of memory can be protected to make

sure that operations occur as written (the penalty is extra cycles that are added to align the operations).

This mode is programmable and, by default, it will protect the selected zones.

On the 2812, at reset, XINTF Zone 7 is accessed if the XMP/MC pin is pulled high. This signal selects

microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high

memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In

microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows

the user to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on

reset is stored in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in

software and hence control the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are

affected by XMP/MC.

I/O space is not supported on the 2812 XINTF.

The wait states for the various spaces in the memory map area are listed in Table 3-3.

Table 3-3. Wait States

AREA

WAIT-STATES

COMMENTS

M0 and M1 SARAMs

0-wait

Fixed

Peripheral Frame 0

0-wait

Fixed

0-wait (writes)

Peripheral Frame 1

Fixed

2-wait (reads)

0-wait (writes)

Peripheral Frame 2

Fixed

2-wait (reads)

L0 and L1 SARAMs

0-wait

Fixed

Programmed via the Flash registers. 1-wait-state operation is possible at a

Programmable,

OTP (or ROM)

reduced CPU frequency. See Section 3.2.6, Flash (F281x Only), for more

1-wait minimum

information.

Programmed via the Flash registers. 0-wait-state operation is possible at

Programmable,

Flash (or ROM)

reduced CPU frequency. The CSM password locations are hardwired for

0-wait minimum

16 wait states. See Section 3.2.6, Flash (F281x Only), for more information.

H0 SARAM

0-wait

Fixed

Boot-ROM

1-wait

Fixed

Programmed via the XINTF registers.

Programmable,

XINTF

Cycles can be extended by external memory or peripheral.

1-wait minimum

0-wait operation is not possible.

Functional Overview

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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

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