ENICSF2811PBKA datasheet(98/172 Pages) TI1

98 / 172 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

SPRS174T – APRIL 2001 – REVISED MAY 2012

www.ti.com

6.8

Power Sequencing Requirements

TMS320F2812/F2811/F2810 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the

CPU, Flash, ROM, ADC, and the I/Os. To ensure the correct reset state for all modules during power up,

there are some requirements to be met while powering up/powering down the device. The current F2812

silicon reference schematics (Spectrum Digital Incorporated eZdsp board) suggests two options for the

power sequencing circuit.

Power sequencing is not needed for C281x devices. In other words, 3.3-V and 1.8-V (or 1.9-V) can ramp

together. C281x can also be used on boards that have F281x power sequencing implemented; however, if

the 1.8-V (or 1.9-V) rail lags the 3.3-V rail, the GPIO pins are undefined until the 1.8-V rail reaches at least

1 V.

•

Option 1:

In this approach, an external power sequencing circuit enables VDDIO first, then VDD and VDD1

(1.8 V or 1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (VDD3VFL) and ADC

(VDDA1/VDDA2/AVDDREFBG) modules are ramped up. While option 1 is still valid, TI has simplified the

requirement. Option 2 is the recommended approach.

•

Option 2:

Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and then

ramp 1.8 V (or 1.9 V) (VDD/VDD1) supply pins.

1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset

signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the

modules inside the device. See Figure 6-11 for power-on reset timing.

•

Power-Down Sequencing:

During power-down, the device reset should be asserted low (8 µs, minimum) before the VDD supply

reaches 1.5 V. This will help to keep on-chip flash logic in reset prior to the VDDIO/VDD power supplies

ramping down. It is recommended that the device reset control from “Low-Dropout (LDO)” regulators or

voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing

(with the aid of additional external components) may be used to meet the power sequencing

requirement. See www.spectrumdigital.com for F2812 eZdsp™ schematics and updates.

Table 6-4. Recommended “Low-Dropout Regulators”

SUPPLIER

PART NUMBER

DESCRIPTION

Dual 500-mA low-dropout regulator (LDO) with sequencing for

Texas Instruments

TPS75005

C2000 (3 Voltage Rail Monitors)

NOTE

The GPIO pins are undefined until VDD = 1 V and VDDIO = 2.5 V.

Electrical Specifications

Submit Documentation Feedback

Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

ENICSF2811PBKA датащи(PDF) 98 Page - Texas Instruments

ENICSF2811PBKA датащи(HTML) 98 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL