ENICSF2811PBKA datasheet(37/172 Pages) TI1

37 / 172 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174T – APRIL 2001 – REVISED MAY 2012

3.2.18 Peripheral Frames 0, 1, 2 (PFn)

The F281x and C281x segregate peripherals into three sections. The mapping of peripherals is as follows:

PF0:

XINTF:

External Interface Configuration Registers (2812 only)

PIE:

PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash:

Flash Control, Programming, Erase, Verify Registers

Timers:

CPU-Timers 0, 1, 2 Registers

CSM:

Code Security Module KEY Registers

PF1:

eCAN:

eCAN Mailbox and Control Registers

PF2:

SYS:

System Control Registers

GPIO:

GPIO Mux Configuration and Control Registers

EV:

Event Manager (EVA/EVB) Control Registers

McBSP:

McBSP Control and TX/RX Registers

SCI:

Serial Communications Interface (SCI) Control and RX/TX Registers

SPI:

Serial Peripheral Interface (SPI) Control and RX/TX Registers

ADC:

12-Bit ADC Registers

3.2.19 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This multiplexing

enables use of a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are

configured as inputs. The user can then individually program each pin for GPIO mode or peripheral signal

mode. For specific inputs, the user can also select the number of input qualification cycles to filter

unwanted noise glitches.

3.2.20 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock

prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter

reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.

When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is

reserved for the DSP/BIOS Real-Time OS, and is connected to INT14 of the CPU. If DSP/BIOS is not

being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be

connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.

3.2.21 Control Peripherals

The F281x and C281x support the following peripherals that are used for embedded control and

communication:

EV:

The event manager module includes general-purpose timers, full-compare/PWM units,

capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event

managers are provided which enable two three-phase motors to be driven or four two-

phase motors. The event managers on the F281x and C281x are compatible to the event

managers on the 240x devices (with some minor enhancements).

ADC:

The ADC block is a 12-bit converter, single ended, 16-channels. It contains two sample-

and-hold units for simultaneous sampling.

Functional Overview

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Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812

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