ENICSF2811PBKA datasheet(62/172 Pages) TI1

62 / 172 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

SPRS174T – APRIL 2001 – REVISED MAY 2012

www.ti.com

4.2.6

PWM Characteristics

Characteristics of the PWMs are as follows:

•

16-bit registers

•

Wide range of programmable deadband for the PWM output pairs

•

Change of the PWM carrier frequency for PWM frequency wobbling as needed

•

Change of the PWM pulse widths within and after each PWM period as needed

•

External-maskable power and drive-protection interrupts

•

Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-

space vector PWM waveforms

•

Minimized CPU overhead using auto-reload of the compare and period registers

•

The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after

PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the

COMCONx register.

–

PDPINTA pin status is reflected in bit 8 of COMCONA register.

–

PDPINTB pin status is reflected in bit 8 of COMCONB register.

•

EXTCON register bits provide options to individually trip control for each PWM pair of signals

4.2.7

Capture Unit

The capture unit provides a logging function for different events or transitions. The values of the selected

GP timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are

detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit

consists of three capture circuits.

Capture units include the following features:

•

One 16-bit capture control register, CAPCONx (R/W)

•

One 16-bit capture FIFO status register, CAPFIFOx

•

Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base

•

Three 16-bit 2-level-deep FIFO stacks, one for each capture unit

•

Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All

inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input

must hold at its current level to meet the input qualification circuitry requirements. The input pins

CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.]

•

User-specified transition (rising edge, falling edge, or both edges) detection

•

Three maskable interrupt flags, one for each capture unit

•

The capture pins can also be used as general-purpose interrupt pins, if they are not used for the

capture function.

4.2.8

Quadrature-Encoder Pulse (QEP) Circuit

Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-

chip QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-

chip. Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or

decremented by the rising and falling edges of the two input signals (four times the frequency of either

input pulse).

With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly,

with EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin.

4.2.9

External ADC Start-of-Conversion

EVA/EVB start-of-conversion (SOC) can be sent to an external pin (EVASOC/EVBSOC) for external ADC

interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively.

Peripherals

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