ENICSF2811PBKA datasheet(33/172 Pages) TI1

33 / 172 page

TMS320F2810, TMS320F2811, TMS320F2812

TMS320C2810, TMS320C2811, TMS320C2812

www.ti.com

SPRS174T – APRIL 2001 – REVISED MAY 2012

3.2.4

Real-Time JTAG and Analysis

The F281x and C281x implement the standard IEEE 1149.1 JTAG interface. Additionally, the F281x and

C281x support real-time mode of operation whereby the contents of memory, peripheral, and register

locations can be modified while the processor is running and executing code and servicing interrupts. The

user can also single step through non-time critical code while enabling time-critical interrupts to be

serviced without interference. The F281x and C281x implement the real-time mode in hardware within the

CPU. This is a unique feature to the F281x and C281x, no software monitor is required. Additionally,

special analysis hardware is provided that allows the user to set hardware breakpoint or data/address

watch-points and generate various user selectable break events when a match occurs.

3.2.5

External Interface (XINTF) (2812 Only)

This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The

chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single

chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed

with a different number of wait states, strobe signal setup and hold timing and each zone can be

programmed for extending wait states externally or not. The programmable wait-state, chip-select and

programmable strobe timing enables glueless interface to external memories and peripherals.

3.2.6

Flash (F281x Only)

The F2812 and F2811 contain 128K x 16 of embedded flash memory, segregated into four 8K x 16

sectors, and six 16K x 16 sectors. The F2810 has 64K x 16 of embedded flash, segregated into two 8K x

16 sectors, and three 16K x 16 sectors. All three devices also contain a single 1K x 16 of OTP memory at

address range 0x3D 7800–0x3D 7BFF. The user can individually erase, program, and validate a flash

sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or

the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is

provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both

program and data space; therefore, it can be used to execute code or store data information.

NOTE

The F2810/F2811/F2812 Flash and OTP wait states can be configured by the application.

This allows applications running at slower frequencies to configure the flash to use fewer

wait states.

Flash effective performance can be improved by enabling the flash pipeline mode in the

Flash options register. With this mode enabled, effective performance of linear code

execution will be much faster than the raw performance indicated by the wait state

configuration alone. The exact performance gain when using the Flash pipeline mode is

application-dependent.

For more information on the Flash options, Flash wait-state, and OTP wait-state registers,

see the TMS320x281x DSP System Control and Interrupts Reference Guide (literature

number SPRU078).

3.2.7

ROM (C281x Only)

The C2812 and C2811 contain 128K x 16 of ROM. The C2810 has 64K x 16 of ROM. In addition to this,

there is a 1K x 16 ROM block that replaces the OTP memory available in flash devices. For information on

how to submit ROM codes to TI, see the TMS320C28x CPU and Instruction Set Reference Guide

(literature number SPRU430).

Functional Overview

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