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DM504 датащи(PDF) 97 Page - Texas Instruments |
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DM504 датащи(HTML) 97 Page - Texas Instruments |
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97 / 211 page ![]() 97 DM504 www.ti.com SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated Table 5-28. DPLL Type A Characteristics NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS finput CLKINP input frequency 0.032 52 MHz FINP finternal Internal reference frequency 0.15 52 MHz REFCLK fCLKINPHIF CLKINPHIF input frequency 10 1400 MHz FINPHIF fCLKINPULOW CLKINPULOW input frequency 0.001 600 MHz Bypass mode: fCLKOUT = fCLKINPULOW / (M1 + 1) if ulowclken = 1(6) fCLKOUT CLKOUT output frequency 20(1) 1400(2) MHz [M / (N + 1)] × FINP × [1 / M2] (in locked condition) fCLKOUTx2 CLKOUTx2 output frequency 40(1) 2200(2) MHz 2 × [M / (N + 1)] × FINP × [1 / M2] (in locked condition) fCLKOUTHIF CLKOUTHIF output frequency 20(3) 1400(4) MHz FINPHIF / M3 if clkinphifsel = 1 40(3) 2200(4) MHz 2 × [M / (N + 1)] × FINP × [1 / M3] if clkinphifsel = 0 fCLKDCOLDO DCOCLKLDO output frequency 40 2800 MHz 2 × [M / (N + 1)] × FINP (in locked condition) tlock Frequency lock time 6 + 350 × REFCLK µs plock Phase lock time 6 + 500 × REFCLK µs trelock-L Relock time—Frequency lock(5) (LP relock time from bypass) 6 + 70 × REFCLK µs DPLL in LP relock time: lowcurrstdby = 1 prelock-L Relock time—Phase lock(5) (LP relock time from bypass) 6 + 120 × REFCLK µs DPLL in LP relock time: lowcurrstdby = 1 trelock-F Relock time—Frequency lock(5) (fast relock time from bypass) 3.55 + 70 × REFCLK µs DPLL in fast relock time: lowcurrstdby = 0 prelock-F Relock time—Phase lock(5) (fast relock time from bypass) 3.55 + 120 × REFCLK µs DPLL in fast relock time: lowcurrstdby = 0 (1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1. For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2. (2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1. (3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down by factor of M3. (4) The maximum frequency on CLKOUTHIF is assuming M3 = 1. (5) Relock time assumes typical operating conditions, 10°C maximum temperature drift. (6) Bypass mode: fCLKOUT = FINP if ulowclken = 0. For more information, see the Device TRM. |
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