DM504 datasheet(80/211 Pages) TI1

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DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Specifications

Table 5-11. LVCMOS CSI2 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

NOM

MAX

UNIT

Signals MUXMODE0 : csi2_0_dx[4:0]; csi2_0_dy[4:0];

Bottom Balls: A5 / B5 / A6 / B6 / B8 / A8 / A10 / B10 / A11 / B11

MIPI D-PHY Mode Low-Power Receiver (LP-RX)

VIH

Input high-level voltage

880

1350

VIL

Input low-level voltage

550

VITH

Input high-level threshold

880

VITL

Input low-level threshold

550

VHYS

Input hysteresis

MIPI D-PHY Mode Ultralow Power Receiver (ULP-RX)

VIH

Input high-level voltage

880

VIL

Input low-level voltage

300

VITH

Input high-level threshold

880

VITL

Input low-level threshold

300

VHYS

Input hysteresis

MIPI D-PHY Mode High-Speed Receiver (HS-RX)

VIDTH

Differential input high-level threshold

VIDTL

Differential input low-level threshold

–70

VIDMAX

Maximum differential input voltage

270

VIHHS

Single-ended input high voltage

460

VILHS

Single-ended input low voltage

–40

VCMRXDC

Differential input common-mode voltage

330

ZID

Differential input impedance

100

125

(1) VITH is the voltage at which the receiver is required to detect a high state in the input signal.

(2) VITL is the voltage at which the receiver is required to detect a low state in the input signal. VITL is larger than the maximum single-ended

line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling.

(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, VHYST. VHYST is the difference

between the VITH threshold and the VITL threshold.

(4) VITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during

ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.

(5) Excluding possible additional RF interference of 200 mVPP beyond 450 MHz.

(6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and

variations below 450 MHz.

(7) This number corresponds to the VODMAX transmitter.

(8) Common mode is defined as the average voltage level of X and Y: VCMRX = (VX + VY) / 2.

(9) Common mode ripple may be due to tR or tF and transmission line impairments in the PCB.

(10) For more information regarding the pin name (or ball name) and corresponding signal name, see Table 4-8 CSI 2 Signal Descriptions.

Table 5-12. CSI2 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

NOM

MAX

UNIT

Signal Names in Mode 0 (Function 1):

Bottom Balls:

1.8-V Mode

VIH

Input high-level threshold

VIL

Input low-level threshold

VHYS

Input hysteresis voltage

VOH

Output high-level threshold (IOH = TBD 2 mA)

VOL

Output low-level threshold (IOL = TBD 2 mA)

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