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DM504 датащи(PDF) 76 Page - Texas Instruments |
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DM504 датащи(HTML) 76 Page - Texas Instruments |
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76 / 211 page ![]() 76 DM504 SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017 www.ti.com Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated 5.6 Power Consumption Summary NOTE Maximum power consumption for this SoC depends on the specific use conditions for the end system. Contact your TI representative for assistance in estimating maximum power consumption for the end system use case. 5.7 Electrical Characteristics NOTE The data specified in Table 5-6 through Table 5-11 are subject to change. NOTE The interfaces or signals described in Table 5-6 through Table 5-11 correspond to the interfaces or signals available in multiplexing mode 0 (Function 1). All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which case different DC electrical characteristics are specified for the different multiplexing modes (Functions). Table 5-6. LVCMOS DDR DC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT Signal Names in MUXMODE 0 (Single-Ended Signals) ABE: ddr1_d[31:0], ddr1_a0, ddr1_a[9:3], ddr1_a[12:11], ddr1_a[15:14], ddr1_dqm[3:0], ddr1_ca[9:0], ddr1_csn[1:0], ddr1_cke[1:0], ddr1_odt[0], ddr1_rst, ddr1_ecc_d[7:0], ddr1_dqm_ecc; Driver Mode VOH High-level output threshold (IOH = 0.1 mA) 0.9*VDDS V VOL Low-level output threshold (IOL = 0.1 mA) 0.1*VDDS V CPAD Pad capacitance (including package capacitance) 3 pF ZO Output impedance (drive strength) l[2:0] = 000 (Imp80) 80 Ω l[2:0] = 001 (Imp60) 60 l[2:0] = 010 (Imp48) 48 l[2:0] = 011 (Imp40) 40 l[2:0] = 100 (Imp34) 34 Single-Ended Receiver Mode VIH High-level input threshold LPDDR2 VREF+0.13 VDDS+0.2 V VIL Low-level input threshold LPDDR2 -0.2 VREF-0.13 V VCM Input common-mode voltage VREF - 1%VDDS VREF+ 1%VDDS V CPAD Pad capacitance (including package capacitance) pF Signal Names in MUXMODE 0 (Differential Signals): ddr1_dqs[3:0], ddr1_dqsn[3:0], ddr1_ck, ddr1_nck, ddr1_dqs_ecc, ddr1_dqsn_ecc; Driver Mode VOH High-level output threshold (IOH = 0.1 mA) 0.9*VDDS V VOL Low-level output threshold (IOL = 0.1 mA) 0.1*VDDS V CPAD Pad capacitance (including package capacitance) 3 pF |
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