DM504 datasheet(86/211 Pages) TI1

86 / 211 page

vdds18v, vdds18v_ddr1, vdds18v_ddr2,

vdds18v_ddr3, vdds18_mem, vdda_spi

I/O Buffer Voltages

vdda_adc, vdda_csi, vdda_dac, vdda_ddr_dsp,

vdda_gmac_core, vdda_osc, vdda_per

vdds_ddr, vdd_mem

vdd

vdd_dspeve

CORE AVS Voltage

DSPEVE AVS Voltage

vddshv1, vddshv2, vddshv3,

vddshv4, vddshv5

(3), vddshv6

PLL and Analog PHY Voltages

EMIF Voltages

resetn, porz

xi_osc0

Valid Config

sysboot[15:0]

rstoutn

Note 3

Note 4

Note 5

Note 6

Note 8

Note 7

Note 9

Note 10

Note 11

SPRS91 _ELCH_01

DM504

SPRS977A – NOVEMBER 2016 – REVISED JANUARY 2017

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Specifications

5.9.3

Power Supply Sequences

This section describes the power-up and power-down sequence required to ensure proper device

operation.

Figure 5-1 and Figure 5-2, describes the Device Power Sequencing.

Figure 5-1. Power-Up Sequencing

(1) Grey shaded areas are windows where it is valid to ramp-up a voltage rail.

(2) Blue dashed lines are not valid windows but show alternate ramp-up possibilities based on whether I/O voltage levels are 1.8V or 3.3V

(see associated note for more details).

(3) vdds18v_* and vdda_* rails should not be combined for best performance to avoid transient switching noise impacts on analog domains.

vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached

until after vdds18v. The preferred sequence is to follow all vdds18v_* to ensure circuit components and PCB design do not cause an

inadvertent violation.

(4) vdds_ddr and vdd_mem should not ramp-up before vdds18v_*. The preferred sequence is to follow all vdds18v_* to ensure circuit

components and PCB design do not cause an inadvertent violation. vdds_ddr* can ramp-up before, concurrently or after vdda_*, there

are no dependencies between vdds_ddr* and vdda_* domains.

–

vdds_ddr* supplies can be combined with vdds18v_* and vdds18v_ddr supplies for DDR2 mode of operation (1.8V) and ramped up

together for simplified power sequencing.

–

If vdds18v_ddr and vdds_ddr* are kept separate from vdds18v_* on board, then this combined DDR supply can come up together

or after the vdds18v_* supply. The DDR supply in this case should never ramp up before the vdds18v_*.

(5) vdd should not ramp-up before vdds18v_* or vdds_ddr* domains.

(6) vdd_dspeve must not exceed vdd core supply and maintain at least 150mV lower voltage on vdd_dspeve vs vdd. vdd_dspeve could

ramp concurrently with vdd if design ensures final operational voltage will not be reached until after vdd and maintains minimum of

150mV less than vdd during entire ramp time. The preferred sequence is to follow vdd to ensure circuit components and PCB design do

not cause an inadvertent violation.

(7) If any of the vddshv[1-6] power rails are used for 1.8V I/O signaling, then these rails can be combined with vdds18v_*.

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