LM2633 datasheet(38/40 Pages) NSC

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Control Loop Design (Continued)

(61)

where V

fb3 is equal to the reference voltage connected to the

non-inverting input of the error amplifier and has a typical

value of 1.24V, and I

fb3 is the bias current drawn by the FB3

pin and has a typical value of 70 nA.

Example: The intended output voltage is 2.5V. Find the

appropriate R

2 value if R1 is chosen to be 10.0 kΩ.

(62)

The G3 voltage cannot exceed 4V, and the G3 current

sourcing capability decreases with increasing G3 pin volt-

age. See the typical curves. It is suggested that the maxi-

mum output voltage does not exceed 3V when an NPN pass

transistor is used. If an N-channel FET is to be used, make

sure the FET can be fully turned on before G3 goes to 4V.

There are two factors to consider when selecting Q

1. First is

the DC current gain

β, second is power dissipation.

For a certain load current, the lower the

β value, the more

base current is necessary to maintain regulation. Since the

base current comes from VIN pin through internal linear

regulation, a large base current significantly increases power

consumption in the LM2633 and hurts light-load efficiency,

particularly when VIN is relatively high. Therefore a transistor

with a large

β value is preferred.

The maximum power consumption in Q

1 is:

loss =Iload_max • (Vin2_max −Vout3_min)

(63)

Example: The input voltage of the linear regulator is 3.3V

±5%, the maximum load current is 150 mA, and the output

voltage is 2.5V. Since Channel 3 of the LM2633 has a ±2%

tolerance over temperature, and the voltage divider contrib-

utes another ±1%, so the total output voltage tolerance is

±3%. See Equation (52) for the calculation of total tolerance

when a voltage divider is used.

loss = 150 mA x (3.3V x 1.05 − 2.5V x 0.97) = 156 mW

If the ambient temperature is 65˚C or less, a SOT-23 pack-

age should be able to handle this much power.

Since Channel 3 affects UVP, if it is not to be used, proper

termination of the pins should be made. One good way is to

tie FB3 to VLIN5, and tie OUT3 and G3 together and leave

them floating. See

Figure 20.

The error amplifier of Channel 3 has a DC gain of 83 dB, and

a unity-gain bandwidth of 200 kHz. See the plots in

Figure

21.

It is not easy to model the loop frequency response of an

NPN linear regulator. The best way is still to measure the

loop gain under different load conditions on bench. As a

reference point, for an LDO set at 2.5V that uses an

MMBT2222 as the pass transistor,a1µF ceramic as the

output capacitor and at a 170 mA load, the bandwidth is

about 107 kHz, with a phase margin of 71˚ and a gain margin

of about 10 dB.

The higher the bandwidth, the less the output capacitance is

needed to handle the load transient. However, for most

applications, stability is the only concern.

PCB Layout Guidelines

It is extremely important to follow the guidelines below to

ensure a clean and stable operation.

Use a four-layer PCB.

Keep the FETs as close to the IC as possible.

Keep the power components on the right side (pins 25

through 48) of the IC and low-power components on the

left side.

Analog ground and power ground should be separate

planes and should be connected at a single point, pref-

erably at the PGNDx and GND pins and directly under-

neath the IC.

The VDDx pin decoupling capacitor should be con-

nected to the power ground plane.

Input ceramic capacitors should be placed very close to

the FETs and their connections to the drain of the top

FET and to the source of the bottom FET should be as

short as possible and should not go through power plane

or ground plane.

HDRVx, SWx traces should be as close to each other as

possible to minimize noise emission. If these two traces

are longer than 2 centimeters, they should be fairly wide,

such as 50mil.

Keep KSx trace as short as possible. Otherwise, use a

trace of 50mil or wider.

ILIMx trace should be kept away from noisy nodes such

as the switch node.

10. It is preferable to have a shorter and wider FBx trace

than a longer and narrower one.

200008A8

FIGURE 20. When Ch.3 is Not in Use

20000895

FIGURE 21. V

FB3-to-VG3 Transfer Function (theoretical)

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