LM2633 datasheet(26/40 Pages) NSC

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Output Capacitor Selection

(Continued)

Because the response speed of the regulator is slow com-

pared to a typical CPU load transient, the regulator has to

rely heavily on the output capacitors to handle the load

transient. The initial overshoot or undershoot is caused by

the ESR of the output capacitors. How the output voltage

recovers after that initial excursion depends on how fast the

output inductor current ramps and how large the output

capacitance is. See

Figure 3. If the total combined ESR of

the output capacitors is not low enough, the initial output

voltage excursion will violate the specification, see

∆V

c1.If

the ESR is low enough, but there is not enough output

capacitance, output voltage will have too much an extra

excursion and travel outside the specification window, before

it returns to its nominal value, see

∆V

c2.

During a load transient, the delta output voltage

∆V

c has two

changing components. One is the delta voltage across the

ESR (

∆V

r), the other is the delta voltage caused by the

gained charge (

∆V

q). Both delta voltages change with time.

For

∆V

r, the equation is:

(1)

and for

∆V

q, the equation is:

(2)

The total change in output voltage during such a load tran-

sient is:

∆V

c = ∆Vr + ∆Vq

(3)

From

Figure 4 it can be told that

∆V

c will reach its peak value

at some point in time and then it is going to decrease. The

larger the output capacitance is, the earlier the peak will

happen. If the capacitance is large enough, the peak will

occur at the beginning of the transient, i.e.,

∆V

c will decrease

monotonically after the transient happens. To find the peak

position, let the derivative of

∆V

c go to zero, and the result is:

(4)

The target is to find the capacitance value that will yield, at

peak,a ∆Vc that equals ∆Vc_s. By plugging tpeak expression

into the

∆V

C expression and equating the latter to ∆Vc_s, the

following formula is obtained:

(5)

Notice it is already assumed the total ESR is no greater than

e_s otherwise the term under the square root will be a

negative value.

There are two scenarios when calculating the C

min. See

Figure 5. One is that R

e is equal to Re_s so there is abso-

lutely no room for

∆V

q, which means tpeak = 0s. The other is

that R

e is smaller than Re_s so there is some room for ∆Vq,

which means t

peak is greater than zero. However, it is not

necessary to differentiate between the two scenarios when

figuring out the C

min by the above formula.

Allowed transient voltage excursion

The allowed output voltage excursion during a load transient

is:

(6)

Example: V

n = 1.35V, δ% = 7.5%, λ% = 1.4%, Vrip = 20mV

Since the ripple voltage is included in the calculation of

∆V

c_s, the inductor ripple current should not be included in

the worst-case load current excursion. That is, the

worst-case load current excursion should be simply

∆I

c_s.

20000807

FIGURE 3. Load Transient Spec. Violation

20000808

FIGURE 4. Delta Output Voltage Components

20000813

FIGURE 5. R

e =Re_s vs Re < Re_s

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