LM2633 datasheet(25/40 Pages) NSC

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Design Procedures (Continued)

ESR - Equivalent Series Resistance.

Loading transient - a load transient when the load current

goes from minimum load to full load.

Unloading transient - a load transient when the load current

goes from full load to minimum load.

C - regulator output capacitance.

D - duty cycle.

f - switching frequency.

nlim - negative current limit level.

ilim - ILIMx pin current.

irrm - maximum input current ripple RMS value.

load - load current.

rip - output inductor peak-to-peak ripple current.

δ% - CPU core voltage regulation window.

λ% - LM2633 initial DAC tolerance.

∆V

c_s - maximum allowed CPU core voltage excursion dur-

ing a load transient, as derived from CPU specifications.

∆I

c_s - maximum load current change during a load transient,

as specified by the CPU manufacturer.

L - inductance of the output inductor.

e - total combined ESR of output capacitors.

e_s - maximum allowed total combined ESR of the output

capacitors, as derived from CPU load transient specifica-

tions.

ilim - current limit adjustment resistance. See Current Sens-

ing and Current Limiting.

max - maximum allowed dynamic VID transition time.

peak - time for the CPU core voltage to reach its peak value

during an unloading transient.

in - input voltage to the switching regulators.

n - nominal output voltage.

old

- nominal CPU core voltage before dynamic VID

change.

new - nominal CPU core voltage after dynamic VID change.

rip - peak-to-peak output ripple voltage.

General

Designing a power supply involves many tradeoffs. A good

design is usually a design that makes good tradeoffs. To-

day’s synchronous buck regulators typically run at a 200kHz

to 300kHz switching frequency. Beyond this range, switching

loss becomes excessive, and below this range, inductor size

becomes unnecessarily large. The LM2633 has a fixed op-

erating frequency of 250kHz when VIN voltage is below

about 17V, and has decreased frequency when VIN voltage

exceeds 17V. See

Active Frequency Control section.

In a mobile CPU application, both the CPU core and the GTL

bus exhibit large and fast load current swings. The load

current slew rate during such a transient is usually well

beyond the response speed of the regulator. To meet the

regulation specification, special considerations should be

given to the component selection. For example, the total

combined ESR of the output capacitors must be lower than a

certain value. Also because of the tight regulation specifica-

tion, only a small budget can be assigned to ripple voltage,

typically less than 20mV. It is found that starting from a given

output voltage ripple will often result in fewer design itera-

tions.

The design procedures that follow are generally appropriate

for both the CPU core and the GTL bus power supplies,

although emphasis is placed on the former. When there is a

difference between the two, it will be pointed out.

Output Capacitor Selection

Type of output capacitors

Different type of capacitors often have different combinations

of capacitance and ESR. High-capacitance multi-layer ce-

ramic capacitors (MLCs) have very low ESR, typically 12m

Ω,

but also relatively low capacitance - up to 100µF. Tantalum

capacitors can have fairly low ESR, such as 18m

Ω, and

pretty high capacitance - up to 1mF. Aluminum capacitors

can have very high capacitance and fairly low ESR. OSCON

capacitors can achieve ESR values that are even lower than

those of MLCs’ while having a higher capacitance.

Tutorial on load transient response

Skip to the next subsection when a quick design is desired.

The control loop of the LM2633 can be made fast enough so

that when a worst-case load transient happens, duty cycle

will saturate (meaning it jumps to either 0% or D

max). If the

control loop is fast enough, the worst situation for a load

transient will be that the transient happens when the follow-

ing three are also happening. One, present PWM pulse has

just finished. Two, input voltage is the highest. Three, the

load current goes from maximum down to minimum (referred

to as an unloading transient).

Figure 2 shows how inductor

current changes during a worst-case load transient. The

reasons are as follows. In a mobile CPU application, the

input/output voltage differential, which is applied across the

inductor during a loading transient, is higher than the output

voltage, which is applied across the inductor during an un-

loading transient.

That means the inductor current changes slower during an

unloading transient than during a loading transient. The

slower the inductor current changes during a load transient,

the higher output capacitance is needed. That is why an

unloading transient is the worst case. If the load transient

happens when the present PWM pulse has just finished, the

inductor current will be the highest, which means highest

initial charging current for the output capacitors. Finally, the

higher the input voltage, the higher the inductor ripple cur-

rent and the higher the initial charging current for the output

capacitors.

20000806

FIGURE 2. Worst-case Load Transient

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