LM2633 datasheet(24/40 Pages) NSC

24 / 40 page

Operation Descriptions (Continued)

output voltage will not be affected unless the UVLO method

is used to release the latch. If the linear channel causes a

UVP event, then the IC enters

Shut Down Latch State.If

later the fault at the linear channel is removed, the linear

channel will recover, but the IC will still be in the latch state.

Over-voltage Protection

This protection feature is implemented in the two switching

channels and not in the linear channel. Refer to

Table 1.As

long as there is at least one switching channel enabled, and

the LM2633 is not in fault state, an over voltage event at

either of the two switching channels’ output will cause sys-

tem to enter the

Shut Down Latch State.

However, if the over voltage event happens only on Channel

1 after a dynamic VID change signal is issued and before the

change completes, the system will not enter the

Shut Down

Latch State. See the Dynamic VID Change section.

Under-voltage Protection

The UVP feature is implemented in all three channels.

If the UV_DELAY pin is pulled to ground, then the under-

voltage protection feature is disabled. Otherwise, if a capaci-

tor is connected between the UV_DELAY pin and ground,

the UVP is enabled. Assume UVP is enabled and the system

is not in fault state. If a switching channel is enabled, and its

soft start time out signal (sstox, see soft start section) is

asserted, then an under voltage event at the output of that

channel will cause the system to enter the

Shut Down Latch

State.

However, if the under voltage event happens only on Chan-

nel 1 after a dynamic VID change signal is issued and before

the change completes, the system will not enter the

Shut

Down Latch State. See the Dynamic VID Change section.

For the linear channel, if there is at least one switching

channel on, and at least one soft start time out signal has

been issued, and if the system is not in

Fault State, then an

under voltage event at the linear regulator output will cause

the system to enter

Shut Down Latch State.

When the LM2633 reacts on an under voltage event,a5µA

current will be charging the capacitor connected to the

UV_DELAY pin and when its voltage exceeds 2.1V, the

system immediately enters

Shut Down Latch State.

For details, see the block diagram and

Shut Down Latch

Truth Table.

Power Good Function

The power good function is a general indication of the health

of the regulators. There is an internal MOSFET tied from the

PGOOD pin to ground. Power good signal is asserted by

turning off that MOSFET.

The internal power good MOSFET will not be turned on

unless at least one of the following occurs:

There is an output over voltage event in at least one of

the switching channels.

The output voltage of any of the three channels is below

the power good lower limit, regardless of ON/SSx pin

voltage level.

Whenever Channel 1 is going through a dynamic VID

change.

System is in the shut down mode.

System is in the fault state.

System is in the shut down latch state.

Power good upper limit is the same as that of the OVP

function.

In cases 2 and 3 above, if the corresponding output volt-

age(s) recovers, PGOOD will be asserted again. But there is

a built-in hysteresis. See V

pwrgd in the Electrical Character-

istics Table. The above information is also available in Power

Good Truth Table.

When the internal power good MOSFET is turned on, the

PGOOD pin will be pulled to ground. When it is turned off,

the PGOOD pin floats (open-drain). The on resistance of the

power good MOSFET is about 15k

Ω.

Dynamic VID Change

During normal operation, if Channel 1 sees a change in the

VID pattern, a NEW VID signal will be issued. Upon seeing

the NEW VID signal, power good signal will be deasserted,

UVP and OVP of Channel 1 will be disabled temporarily, and

Channel 1 goes through a special step to quickly ramp the

output voltage to the new value.

If the new output voltage is higher than the old voltage,

Channel 1 will rely on the control loop to change the output

voltage. If the new value is lower than the old one, the top

FET is going to remain off while the bottom FET is going to

remain on. This will cause the output capacitor to discharge

through the inductor. The 0-CROSSING / NEGATIVE CUR-

RENT LIMIT comparator will detect for negative over current,

even if the LM2633 is in pulse-skip mode. When the negative

current limit is reached, bottom FET will be turned off, forcing

the inductor current to flow through the body diode of the top

FET to the input supply. When next clock cycle comes, the

bottom FET will be turned on again, and it will not be turned

off until the negative current limit is reached again. During

this process, if the output voltage goes below the new volt-

age, the NEW VID signal will be deasserted. At this time,

power good function will be released, OVP and UVP will be

enabled and the bottom FET will be turned off. The normal

control loop takes over after the output voltage droops below

the new DAC voltage.

Internal 5V Supply

The internal 5V supply is generated from the VIN voltage

through an internal linear regulator. This 5V supply is mainly

for internal circuitry use, but can also be used externally

(through the VLIN5 pin) for convenience. A typical use of this

5V is supplying the bootstrap circuitry for top drivers and

supplying the voltage needed by the bottom drivers (through

the VDDx pins). But since this 5V is generated by a linear

regulator, it may hurt the light load efficiency, especially

when VIN voltage is high. So if there is a separate 5V

available that is generated by a switching power supply, it

may be a good idea to use that 5V to power the bootstrap

circuitry and the VDDx pins for better efficiency and less

thermal stress on the LM2633.

In shut down mode, the VLIN5 pin will go to 5.5V. So it is

recommended not to use this voltage for purposes other

than the bootstrap circuitry and VDDx pins.

When the power stage input voltage can be guaranteed to

be within 4.5V to 5.5V, the VLIN5 pin can be tied to the VIN

pin directly. In this mode, all 5V currents are directly coming

from power stage input rail VIN and power loss due to the

internal linear regulation is no longer an issue.

Design Procedures

CPU Core / GTL Bus Power Supply

Nomenclature

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