LM2633 datasheet(32/40 Pages) NSC

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Control Loop Design (Continued)

(39)

The value of f

p can be determined by comparing the denomi-

nators of

Equation (35) and Equation (27). The result is:

(40)

From the above expressions, it can be seen that the

control-output transfer function has three poles and one

zero. Of the three poles, one is a real pole (f

p) that is located

at low frequency, the other two are either complex conju-

gates that are located at half the switching frequency (f

n), or

are separated real poles, depending on the Q value. When Q

value is less than 0.5, the two high frequency poles will

become two real poles.

From

Equation (34) it can be told that Q will become nega-

tive when m

< 1/(2D’). A negative Q value means an

unstable system because the control-output transfer function

will have a right-half-plane pole.

Example: L = 1.5 µH, C = 2 mF, R

e =9 mΩ,Rds =10 mΩ,

in = 10V, Vout = 1.6V, R = 0.4Ω. For LM2633, f = 250 kHz,

e = 0.25V, ρ =5.

j = 10mΩ x 5 = 50mΩ

e = 0.25V x 250kHz = 62.5mV/µs

n = 250kHz ÷ 2 = 125kHz

The resulting gain plot is shown in

Figure 9 as the asymptotic

plot. The plots of the actual gain and phase as computed by

Equation (27) are also shown.

It should be noted that load resistance only changes the low

frequency gain. This causes the location of the low fre-

quency pole to change with load.

Frequency Compensation Design

The general purpose to compensate the loop is to meet

static and dynamic performance requirements while main-

taining stability. Loop gain is what is usually checked for

small-signal performance. Loop gain is equal to the product

of control-output transfer function (or so-called ’plant’) and

the output-control transfer function (i.e. the compensation

network transfer function). Different compensation schemes

result in different trade-offs among static accuracy, transient

response speed and degree of stability, etc.

Generally speaking it is a good idea to have a loop gain

slope that is −20dB/decade from a very low frequency to well

beyond cross-over frequency. The cross-over frequency

should not exceed one-fifth of the switching frequency, i.e.

50kHz in the case of LM2633. The higher the bandwidth, the

potentially faster the load transient response speed. How-

ever, if the duty cycle saturates during the load transient,

then further increasing the small signal bandwidth will not

help. In the context of CPU core or GTL bus power supply, a

small-signal bandwidth of 20kHz to 30kHz should be suffi-

cient if output capacitors are not just MLCs.

Since the control-output transfer function usually has very

limited low frequency gain (see

Figure 9), it is a good idea to

place a pole in the compensation at zero frequency, so that

the low frequency gain especially the DC gain will be very

large. A large DC gain means high DC regulation accuracy

(i.e. DC voltage changes little with load or line variations).

The rest of the compensation scheme depends highly on the

plant shape. If a typical shape such as shown in

Figure 9 is

assumed, then the following can be done to create a

−20dB/decade roll-off of the loop gain.

Place the first zero at f

p, the second pole at fz, and the

second zero at f

n, then the resulting loop gain plot will be of

−20dB/dec slope from zero frequency up to f

n (half the

switching frequency).

Figure 10 shows the gain plot of such a two-pole two-zero

(more accurately, a lag-lag) compensation network, where

z1,fz2 and fp2 are the first zero, second zero and second

pole frequencies. The first pole f

p1 is located at zero fre-

quency.

20000863

FIGURE 9. Example Control-Output Transfer Function

Bode Plot

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