LM2633 datasheet(27/40 Pages) NSC

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Output Capacitor Selection

(Continued)

Maximum ESR calculation

No matter how much capacitance there is, if the total com-

bined ESR is not less than a certain value, the load transient

requirement will not be met.

The maximum allowed total combined ESR is:

(7)

Example:

∆V

c_s = 72mV, ∆Ic_s = 10A. Then Re_s = 7.2mΩ.

Maximum ESR criterion can be used when the capacitance

is high enough, otherwise more capacitors than the number

determined by this criterion should be used.

Minimum capacitance calculation

In a CPU core or a GTL bus power supply, the minimum

output capacitance is typically dictated by the load transient

requirement. If there is not enough capacitance, the output

voltage excursion will exceed the maximum allowed value

even if the maximum ESR requirement is met. The

worst-case load transient is an unloading transient that hap-

pens when the input voltage is the highest and when the top

FET has just been turned off. The corresponding minimum

capacitance is calculated as follows:

(8)

Notice it is already assumed the total ESR is no greater than

e_s, otherwise the term under the square root will be a

negative value.

Example: R

e =6mΩ,Vn = 1.35V, ∆Vc_s = 72mV, ∆Ic_s =

10A, L = 2µH

Generally speaking, C

min decreases with decreasing Re,

∆I

c_s, and L, but with increasing Vn and ∆Vc_s.

Maximum capacitance calculation

This subsection applies to Channel 1 / CPU core power

supply only.

If there is a need to change the CPU core voltage dynami-

cally (see Dynamic VID Change), there will be a maximum

output capacitance restriction. If the output capacitance is

too large, it will take too much time for the CPU core voltage

to ramp to the new value, violating the maximum transition

time specification. The worst-case dynamic VID change is

one that takes the largest step down at no load. The maxi-

mum capacitance as determined by the way LM2633 imple-

ments the VID change can be calculated as follows:

(9)

Example: t

max = 100µs, Inlim = 20A, Vold = 1.6V, Vnew =

1.35V, I

load =0.

Generally speaking, C

max decreases with decreasing tmax,

nlim and Iload, but with increasing voltage step.

Power loss in output capacitors

In a typical buck regulator, the ripple current in the inductor

(and thus the output capacitors) is so small that it causes

very little power loss. The equation for calculating that loss

is:

(10)

Example: I

rip = 4.3A, Re =7 mΩ.

(11)

Output Inductor Selection

The size of the output inductor can be determined from the

assigned output ripple voltage budget and the impedance of

the output capacitors at switching frequency. The equation to

determine the minimum inductance value is as follows:

(12)

where min(V

in_max, 17V) means the smaller of Vin_max and

17V. The reason this term is not simply V

in_max is that the

switching frequency droops with increasing V

in when Vin is

higher than 17V. See Active Frequency Control.

In the above equation, R

e is used in place of the impedance

of the output capacitors. This is because in most cases, the

impedance of the output capacitors at the switching fre-

quency is very close to R

e. In the case of ceramic capacitors,

replace R

e with the true impedance.

Example 1: V

in_max = 21V, Vn = 1.6V, Vrip = 26mV, Re =

Ω, f = 250kHz.

Example 2: V

in_max = 18V, Vn = 1.35V, Vrip = 20mV, Re =

Ω, f = 250kHz.

The actual selection process usually involves several itera-

tions of all of the above steps, from ripple voltage selection,

to capacitor selection, to inductance calculations. Both the

highest and the lowest CPU core voltages and their load

transient requirements should be considered. If an induc-

tance value larger than L

min is selected, make sure the Cmin

requirement is not violated. Priority should be given to pa-

rameters that are not flexible or more costly. For example, if

there are very few types of capacitors to choose from, it may

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