DSP56156ROM datasheet(3/76 Pages) MOTOROLA

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MOTOROLA

DSP56156 Data Sheet

Introduction

• On-chip peripheral registers memory mapped in data memory space

• Double buffered peripherals

• Up to 27 general purpose I/O pins

• Two external interrupt request pins

• On-Chip Emulation (OnCE™) port for unobtrusive, processor speed-independent

debugging

• Software-programmable, Phase-Locked Loop-based (PLL) frequency synthesizer for the

core clock

Miscellaneous Features

• Power-saving Wait and Stop modes

• Fully static, HCMOS design for operating frequencies from 40 or 60 MHz down to DC

• 112-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; 20

× 20 × 3 mm

• 112-pin Plastic Thin Quad Flat Pack (TQFP) surface-mount package; 20

× 20 × 1.5 mm

• 5 V power supply

Product Documentation

This data sheet plus the two manuals listed in Table 1 are required for a complete DSP56156

description and are necessary to properly design with the part. Documentation is available

from a local Motorola distributor, a semiconductor sales office, or through a Motorola Litera-

ture Distribution Center.

Table 1 DSP56156 Documentation

Topic

Description

Order Number

DSP56100 Family Manual

Detailed description of the 56000-

family architecture and the 16-bit core

processor and instruction set

DSP56100FAMUM/AD

DSP56156 User’s Manual

Detailed description of memory,

peripherals, and interfaces

DSP56156UM/AD

DSP56156 Data Sheet

Pin and package descriptions, and

electrical and timing specifications

DSP56156/D

DSP56156 Features

Documentation

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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