DSP56156ROM datasheet(9/76 Pages) MOTOROLA

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Pin Descriptions

MOTOROLA

DSP56156 Data Sheet

the BB pin is deasserted. The DSP con-

tinues executing instructions only if in-

ternal program and data memory

resources are accessed. If the DSP re-

quests the external bus while BR input

pin is asserted, the DSP bus controller

inserts wait states until the external bus

becomes available (BR and BB deas-

serted). Note that interrupts are not

serviced when a DSP instruction is

waiting for the bus controller. Note

also that BR is prevented from inter-

rupting the execution of a read/ modi-

fy/write instruction.

If the master bit in the OMR register is

set, this pin becomes an output (Master

Mode). In this mode, the DSP is not the

external bus master and has to assert

BR to request the bus mastership. The

DSP bus controller will insert wait

states until BG input is asserted and

will then begin normal bus accesses af-

ter the rising of the clock which sam-

pled BB high. The BR output signal will

remain asserted until the DSP no long-

er needs the bus. In this mode, the Re-

quest Hold bit (RH) of the Bus Control

under software control.

During external accesses caused by an

instruction executed out of external pro-

gram memory, BR remains asserted low

for consecutive external X memory ac-

cesses and continues toggling for con-

secutive external P memory accesses

unless the Request Hold bit (RH) is set

inside the Bus Control Register (BCR).

In the master mode, BR can also be

used for non arbitration purpose: if BG

is always asserted, BR is asserted in t0

of every external bus access. It can then

be used as a chip select to turn a exter-

nal memory device off and on between

internal and external bus accesses. BR

timing is in that case similar to A0-A15,

R/W and PS/DS; it is asserted and

deasserted during t0.

BG (Bus Grant) — active low input when

in master mode, active low output

when in slave mode.

Output after

power on reset if the slave is selected,

this pin is asserted to acknowledge an

external bus request. It indicates that

the DSP will release control of the ex-

ternal address bus A0-A15, data bus

D0-D15 and bus control pins when BB

is deasserted. The BG output is assert-

ed in response to a BR input. When the

BG output is asserted and BB is deas-

serted, the external address bus A0-A15,

data bus D0-D15 and bus control pins

are in the high impedance state. BG as-

sertion may occur in the middle of an

instruction which requires more than

one external bus cycle for execution.

Note that BG assertion will not occur

during indivisible read-modify-write

instructions (BFSET, BFCLR, BFCHG).

When BR is deasserted, the BG output

is deasserted and the DSP regains con-

trol of the external address bus, data

bus, and bus control pins when the BB

pin is sampled high.

This pin becomes an input if the master

bit in the OMR register is set (Master

Mode). It is asserted by an external pro-

cessor when the DSP may become the

bus master. The DSP can start normal

external memory access after the BB pin

has been deasserted by the previous

bus master. When BG is deasserted, the

DSP will release the bus as soon as the

current transfer is completed. The state

of BG may be tested by testing the BS bit

in the Bus Control Register. BG is ig-

nored during hardware reset.

Bus Control

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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