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DSP56156ROM датащи(PDF) 5 Page - Motorola, Inc |
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DSP56156ROM датащи(HTML) 5 Page - Motorola, Inc |
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5 / 76 page ![]() MOTOROLA DSP56156 Data Sheet 5 Introduction Pin Groupings The DSP56156 is available in a 112-pin Ceramic Quad Flat Pack (CQFP) and a 112-pin Plastic Thin Quad Flat Pack (TQFP). The input and output signals are organized into the functional groups indicated in Table 3. Figure 2 illustrates the chip’s pin functions. NOTE: OVERBARS are used throughout this document to indicate a signal which is at Ground voltage (typi- cally a TTL logic low — VIL or VOL) when the function is logically true. These signals are, likewise, at VCC voltage (typically a TTL logic high — VIH or VOH) when the function is logically false. Table 3 Functional Pin Groupings Functional Group Number of Pins Address 16 Data Bus 16 Bus Control 9 Host Interface (HI) 15 Synchronous Serial Interfaces (SSI) 10 Timer Interface 2 Interrupt and Mode Control 4 Phase-Locked Loop (PLL) and Clock 3 On-Chip Emulation (OnCETM Port) 4 On-Chip Codec 7 Power (VCC)10 Ground (GND) 16 Total 112 Pin Groupings Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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