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DSP56156ROM датащи(PDF) 1 Page - Motorola, Inc |
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DSP56156ROM датащи(HTML) 1 Page - Motorola, Inc |
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1 / 76 page ![]() © MOTOROLA INC., 1994 MOTOROLA TECHNICAL DATA SEMICONDUCTOR The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP). On a single semi- conductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, pro- gram and data memories, a number of peripherals, and system support circuitry. Unique features of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL). This com- bination of features makes the DSP56156 a cost-effective, high-performance solution for many DSP applications, especially speech coding, digital communications, and cellular base stations. The central processing unit of the DSP56156 is the DSP56100 core processor. Like all DSP56100- based DSPs, the DSP56156 consists of three execution units operating in parallel, allowing up to six operations to be performed during each instruction cycle. This parallelism greatly increases the effective processing speed of the DSP56156. The MPU-style programming model and instruction set allow straightforward generation of efficient, compact code. The basic architectures and devel- opment tools of Motorola's 16-bit, 24-bit, and 32-bit DSPs are so similar that understanding how to design and program one greatly reduces the time needed to learn the others. On-Chip Emulation (OnCETM port) circuitry provides convenient and inexpensive debug facil- ities normally available only through expensive external hardware. Development costs are re- duced and in-field testing is greatly simplified using the OnCETM port. Figure 1 illustrates the DSP56156 in detail. Figure 1 DSP56156 Block Diagram Specifications and information herein are subject to change without notice. OnCE is a trademark of Motorola, Inc. Data 16 Control 9 Address 16 Data ALU 16 x 16 + 40 —> 40-bit MAC Two 40-bit Accumulators PLL Clock Gen. GDB PDB XDB Internal Data Bus Switch External Data Bus Switch Bus Control PAB XAB1 XAB2 Address Generation Unit External Address Bus Switch IRQ 2 16-bit Bus 16-bit 56100 DSP Core Program Address Generator Program Decode Controller Interrupt Control Program Control Unit Sigma- Delta Codec 4 3 OnCE™ Port 16-bit Timer/ Event Counter Sync. Serial (SSI) or I/O Host Interface (HI) or I/O 5 15 2 (boot) Sync. Serial (SSI) or I/O 5 7 Data Memory 2048 × 16 RAM Program Memory * 2048 × 16 RAM 64 × 16 ROM * 12 k x 16 ROM replaces the program RAM on the DSP56156ROM Advance Information 16-bit Digital Signal Processor DSP56156 Order this document by DSP56156/D REV 1 DSP56156ROM Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
Аналогичный номер детали - DSP56156ROM |
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Аналогичное описание - DSP56156ROM |
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