DSP56156ROM datasheet(22/76 Pages) MOTOROLA

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AC Electrical Characteristics and Timing

DSP56156 Data Sheet

MOTOROLA

Reset, Stop, Wait, Mode Select, and Interrupt Timing

(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)

cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles

ws = Number of wait states programmed into external bus access using BCR (WS = 0 - 31)

Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Num

Characteristics

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

RESET Assertion to Address, Data and

Control Signals High Impedance

—25

—

Minimum Stabilization Duration

(See Note 1)

OMR bit 6=0

OMR bit 6=1

600KT

60T

—

600KT

60T

—

600KT

60T

—

Asynchronous RESET Deassertion to

First External Address Output

(See Note 7)

16T

18T+20

16T

18T+17

16T

18T+15

Synchronous Reset Setup Time from

RESET Deassertion to Rising Edge of

CLKO

cyc-4

cyc-3

cyc-2

Synchronous Reset Delay Time from

CLKO High to the First External Access

(See Note 7)

16T+3

16T+20

16T+ 3

16T+18

16T+3

16T+16

Mode Select Setup Time

—

Mode Select Hold Time

0—

—

Edge-triggered Interrupt Request Width

—

Delay from IRQA, IRQB Assertion to

External Data Memory Access Out Valid

- Caused by First Interrupt

Instruction Fetch

- Caused by First Interrupt

Instruction Execution

11T+4

19T+4

—

11T+4

19T+4

—

11T+3

19T+3

—

Delay from IRQA, IRQB Assertion to

General Purpose Output Valid Caused

by the Execution of the First Interrupt

Instruction

22T+5

—

22T+4

—

22T+3

—

Delay from External Data Memory

Address Output Valid Caused by First

Interrupt Instruction Execution to Inter-

rupt Request Deassertion for Level Sen-

sitive Fast Interrupts (See Note 2)

—5T-26

cyc

× ws

—5T-24

cyc

× ws

—5T-22

cyc

× ws

Reset, Stop, Wait, Mode Select, and Interrupt Timing

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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