DSP56156ROM datasheet(39/76 Pages) MOTOROLA

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AC Electrical Characteristics and Timing

MOTOROLA

DSP56156 Data Sheet

Host Port Timing

(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)

T = ICYC / 4

cyc = Clock cycle = 1/2 instruction cycle= 2 T cycle

tHSDL = Host Synchronization Delay Time

(See Note 1)

tsuh = Host Processor Data Setup Time

Active low lines should be “pulled up” in a manner consistent with the AC and DC specifica-

tions.

Table 19 Host Port Timing

Num

Characteristic

40 MHz

50 MHz

60 MHz

Unit

Min

Max

Min

Max

Min

Max

100

tHSDL Host Synchronous Delay

(See Note 1)

3TT3T

101

HEN/HACK Assertion Width

• CVR, ICR, ISR Read

• Read

• Write

(See Notes 2, 4)

2T+36

32+tsuh

—

2T+33

29+tsuh

—

2T+30

26+tsuh

—

102

HEN/HACK Deassertion Width

(See Note 2)

—

103

Minimum Cycle Time Between Two

HEN Assertion for Consecutive

CVR, ICR, ISR Reads

4T+36

—

4T+33

—

4T+30

—

104

Host Data Input Setup Time before

HEN/HACK Deassertion

5—

—

105

Host Data Input Hold Time after

HEN/HACK Deassertion

7—

—

106

HEN/HACK Assertion to Output

Data Active from High Impedance

0—

—

107

HEN/HACK Assertion to Output

Data Valid

—32

—

108

HEN/HACK Deassertion to Output

Data High Impedance

—

18.5

—

109

Output Data Hold Time after

HEN/HACK Deassertion

5—

—

Host Port Timing

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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