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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN9115 датащи(PDF) 97 Page - Microchip Technology |
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LAN9115 датащи(HTML) 97 Page - Microchip Technology |
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97 / 114 page  2005-2016 Microchip Technology Inc. DS00002269A-page 97 LAN9115 6.2 PIO Reads PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are latched at the beginning of the read cycle. Read data is valid as indicated in the timing diagram. PIO reads can be per- formed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between cycles for the period specified. Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read cycles. FIGURE 6-1: LAN9115 PIO READ CYCLE TIMING Note: The “Data Bus” width is 16 bits. TABLE 6-3: PIO READ TIMING Symbol Description MIN TYP MAX Units tcycle Read Cycle Time 165 ns tcsl nCS, nRD Assertion Time 32 ns tcsh nCS, nRD Deassertion Time 13 ns tcsdv nCS, nRD Valid to Data Valid 30 ns tasu Address Setup to nCS, nRD Valid 0 ns tah Address Hold Time 0 ns tdon Data Buffer Turn On Time 0 ns tdoff Data Buffer Turn Off Time 7 ns tdoh Data Output Hold Time 0 ns Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. Data Bus nCS, nRD A[7:1] |
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