LAN9115 datasheet(64/114 Pages) MICROCHIP

64 / 114 page

LAN9115

DS00002269A-page 64

 2005-2016 Microchip Technology Inc.

5.3.5

BYTE_TEST—BYTE ORDER TEST REGISTER

This register can be used to determine the byte ordering of the current configuration

5.3.6

FIFO_INT—FIFO LEVEL INTERRUPTS

This register configures the limits where the FIFO Controllers will generate system interrupts.

TX Data FIFO Available Interrupt (TDFA_INT_EN)

R/W

TX Status FIFO Full Interrupt (TSFF_INT_EN)

R/W

TX Status FIFO Level Interrupt (TSFL_INT_EN)

R/W

RX Dropped Frame Interrupt Enable (RXDF_INT_EN)

R/W

Reserved

RX Status FIFO Full Interrupt (RSFF_INT_EN)

R/W

RX Status FIFO Level Interrupt (RSFL_INT_EN)

R/W

2-0

GPIO [2:0] (GPIOx_INT_EN).

R/W

000

Offset:

64h

Size:

32 bits

Bits

Description

Type

Default

31:0

Byte Test

87654321h

Offset:

68h

Size:

32 bits

Bits

Description

Type

Default

31-24

TX Data Available Level. The value in this field sets the level, in number of

64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be

generated. When the TX data FIFO free space is greater than this value a

TX FIFO Available interrupt (TDFA) will be generated.

R/W

48h

23-16

TX Status Level. The value in this field sets the level, in number of

DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be

generated. When the TX Status FIFO used space is greater than this value

an TX Status FIFO Level interrupt (TSFL) will be generated.

R/W

00h

15-8

Reserved

7-0

RX Status Level. The value in this field sets the level, in number of

DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be

generated. When the RX Status FIFO used space is greater than this value

an RX Status FIFO Level interrupt (RSFL) will be generated.

R/W

00h

Bits

Description

Type

Default

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