LAN9115 datasheet(74/114 Pages) MICROCHIP

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LAN9115

DS00002269A-page 74

 2005-2016 Microchip Technology Inc.

5.3.16

GPT_CNT-GENERAL PURPOSE TIMER CURRENT COUNT REGISTER

This register reflects the current value of the GP Timer.

5.3.17

WORD_SWAP—WORD SWAP CONTROL

This register controls how words from the host data bus are mapped to the CRSs and Data FIFOs inside the LAN9115.

The LAN9115 always sends data from the Transmit Data FIFO to the network so that the low order word is sent first,

and always receives data from the network to the Receive Data FIFO so that the low order word is received first.

5.3.18

FREE_RUN—FREE-RUN 25MHZ COUNTER

This register reflects the value of the free-running 25MHz counter.

Offset:

90h

Size:

32 bits

Bits

Description

Type

Default

31-16

Reserved

15-0

General Purpose Timer Current Count (GPT_CNT). This 16-bit field

reflects the current value of the GP Timer.

FFFFh

Offset:

98h

Size:

32 bits

Bits

Description

Type

Default

31:0

Word Swap. If this field is set to 00000000h, or anything except

FFFFFFFFh, the LAN9115 maps words with address bit A[1]=1 to the high

order words of the CSRs and Data FIFOs, and words with address bit A[1]=0

to the low order words of the CSRs and Data FIFOs. If this field is set to

FFFFFFFFh, the LAN9115 maps words with address bit A[1]=1 to the low

order words of the CSRs and Data FIFOs, and words with address bit A[1]=0

to the high order words of the CSRs and Data FIFOs.

R/W

NASR

00000000h

Offset:

9Ch

Size:

32 bits

Bits

Description

Type

Default

31:0

Free Running SCLK Counter (FR_CNT):

Note:

This field reflects the value of a free-running 32-bit counter. At

reset the counter starts at zero and is incremented for every

25MHz cycle. When the maximum count has been reached the

counter will rollover. Since the bus interface is 16-bits wide, and

this is a 32-bit counter, the count value is latched on the first read.

• The FREE_RUN counter can take up to 160nS to clear after a reset

event.

• This counter will run regardless of the power management states D0, D1

or D2.

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