LAN9115 datasheet(9/114 Pages) MICROCHIP

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 2005-2016 Microchip Technology Inc.

DS00002269A-page 9

LAN9115

TABLE 2-1:

HOST BUS INTERFACE SIGNALS

Pin No.

Name

Symbol

Buffer

Type

# Pins

Description

43-46,49-

53,56-59,62-

Host Data

D[15:0]

I/O8

Bi-directional data port.

12-18

Host Address

A[7:1]

7-bit Address Port. Used to select

Internal CSR’s and TX and RX FIFOs.

Read Strobe

nRD

Active low strobe to indicate a read

cycle.

Write Strobe

nWR

Active low strobe to indicate a write

cycle. This signal, qualified with nCS, is

also used to wakeup the LAN9115 when

it is in a reduced power state.

Chip Select

nCS

Active low signal used to qualify read

and write operations. This signal

qualified with nWR is also used to

wakeup the LAN9115 when it is in a

reduced power state.

Interrupt

Request

IRQ

O8/OD8

Programmable Interrupt request.

Programmable polarity, source and

buffer types.

FIFO Select

FIFO_SEL

When driven high all accesses to the

LAN9115 are to the RX or TX Data

FIFOs. In this mode, the A[7:3] upper

address inputs are ignored.

TABLE 2-2:

DEFAULT ETHERNET SETTINGS

Default Ethernet Settings

SPEED_SEL

Speed

Duplex

Auto Neg.

10MBPS

HALF-DUPLEX

DISABLED

100MBPS

HALF-DUPLEX

ENABLED

TABLE 2-3:

LAN INTERFACE SIGNALS

Pin No.

Name

Symbol

Buffer

Type

# Pins

Description

TXP

TPO+

Twisted Pair Transmit Output, Positive

TXN

TPO-

Twisted Pair Transmit Output, Negative

RXP

TPI+

Twisted Pair Receive Input, Positive

RXN

TPI-

Twisted Pair Receive Input, Negative

PHY External Bias

Resistor

EXRES1

Must be connected to ground through a

12.4K ohm 1% resistor.

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