LAN89218 datasheet(13/148 Pages) MICROCHIP

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 2008-2015 Microchip Technology Inc.

DS60001255B-page 13

LAN89218

General Purpose

I/O data,

nLED1 (Speed

Indicator),

nLED2 (Link &

Activity Indicator),

nLED3 (Full-

Duplex Indicator).

GPIO[2:0]/

nLED[3:1]

IS/O12/

OD12

General Purpose I/O data: These three general-

purpose signals are fully programmable as either

push-pull output, open-drain output or input by

writing the GPIO_CFG configuration register in

the CSR’s. They are also multiplexed as GP LED

connections.

GPIO signals are Schmitt-triggered inputs. When

configured as LED outputs these signals are

open-drain and the input buffers are disabled.

nLED1 (Speed Indicator). This signal is driven

low when the operating speed is 100 Mbps.

During auto-negotiation, when the cable is dis-

connected, and during 10 Mbps operation, this

signal is driven high.

nLED2 (Link & Activity Indicator). This signal is

driven low (LED on) when the LAN89218 detects

a valid link. This signal is pulsed high (LED off) for

80 ms whenever transmit or receive activity is

detected. This signal is then driven low again for a

minimum of 80 ms, after which time it will repeat

the process if TX or RX activity is detected. Effec-

tively, LED2 is activated solid for a link. When

transmit or receive activity is sensed LED2 will

flash as an activity indicator.

nLED3 (Full-Duplex Indicator). This signal is

driven low when the link is operating in full-duplex

mode.

RBIAS

PLL Bias: Connect to an external 12.0 kΩ 1.0%

resistor to ground. Used for the PLL Bias circuit.

Test Pin

ATEST

This pin must be connected to VDD for normal

operation.

Internal Regula-

tor Power

VREG

3.3 V input for internal voltage regulator

+3.3 V I/O Power

VDD_IO

+3.3 V I/O logic power supply pins

I/O Ground

GND_IO

Ground for I/O pins

+3.3 V Analog

Power

VDD_A

+3.3 V analog power supply pins.

Analog Ground

VSS_A

Ground for analog circuitry

Core Voltage

Decoupling

VDD_CORE

+1.8 V from internal core regulator. Both pins

must be connected together externally. Each pin

requires a 0.01 µF decoupling capacitor. In addi-

tion, pin 3 requires a bulk 10uF capacitor (<2 Ω

ESR) in parallel (see Note 1).

Core Ground

GND_CORE

Ground for internal digital logic

PLL Power

VDD_PLL

+1.8 V Power from the internal PLL regulator.

This pin must be connected to a 10 µF capacitor

(<2 Ω ESR), in parallel with a 0.01 µF capacitor to

ground (see Note 2).

PLL Ground

VSS_PLL

GND for the PLL

Reference Power

VDD_REF

Connected to 3.3 V power and used as the refer-

ence voltage for the internal PLL

TABLE 2-4:

SYSTEM AND POWER SIGNALS (CONTINUED)

Name

Symbol

Buffer Type

# Pins

Description

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