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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN89218 датащи(PDF) 87 Page - Microchip Technology |
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LAN89218 датащи(HTML) 87 Page - Microchip Technology |
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87 / 148 page  2008-2015 Microchip Technology Inc. DS60001255B-page 87 LAN89218 3 PME indication (PME_IND). The PME signal can be configured as a pulsed output or a static signal, which is asserted upon detection of a wake-up event. When set, the PME signal will pulse active for 50 ms upon detection of a wake- up event. When clear, the PME signal is driven continuously upon detection of a wake-up event. The PME signal can be deactivated by clearing the WUPS bits, or by clearing the appropriate enable (refer to Section 3.10.2.3). R/W 0b 2 PME Polarity (PME_POL). This bit controls the polarity of the PME signal. When set, the PME output is an active high signal. When reset, it is active low. When PME is configured as an open-drain output this field is ignored, and the output is always active low. R/W NASR 0b 1 PME Enable (PME_EN). When set, this bit enables the external PME signal. This bit does not affect the PME interrupt (PME_INT). R/W 0b 0 Device Ready (READY). When set, this bit indicates that LAN89218 is ready to be accessed. This register can be read when LAN89218 is in any power management mode. Upon waking from any power management mode, includ- ing power-up, the host processor can interrogate this field as an indication when LAN89218 has stabilized and is fully alive. Reads and writes of any other address are invalid until this bit is set. Note: With the exception of HW_CFG and PMT_CTRL, read access to any internal resources is forbidden while the READY bit is cleared. RO - Bits Description Type Default |
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