LAN89218 datasheet(33/148 Pages) MICROCHIP

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DS60001255B-page 33

LAN89218

3.8

General Purpose Timer (GP Timer)

The General Purpose Timer is a programmable block that can be used to generate periodic host interrupts. The

resolution of this timer is 100 µs.

The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting down when

the TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from set ‘1’ to cleared ‘0,’ the

GPT_LOAD field is initialized to FFFFh. The GPT_CNT register is also initialized to FFFFh on a reset. Software can

write the pre-load value into the GPT_LOAD field at any time; e.g., before or after the TIMER_EN bit is asserted.

The GPT Enable bit TIMER_EN is located in the GPT_CFG register.

Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is written to the

GPT_LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT interrupt status bit and the IRQ

signal if the GPT_INT_EN bit is set, and continues counting. The GPT interrupt status bit is in the INT_STS Register.

The GPT_INT hardware interrupt can only be set if the GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e.,

once the GPT_INT bit is set, it can only be cleared by writing a ‘1’ to the bit.

3.9

EEPROM Interface

The LAN89218 can optionally load its MAC address from an external serial EEPROM. If a properly configured

EEPROM is detected by the LAN89218 at power-up, hard reset or soft reset, the ADDRH and ADDRL registers will

be loaded with the contents of the EEPROM. If a properly configured EEPROM is not detected, it is the responsibility

of the host LAN Driver to set the IEEE addresses.

The LAN89218 EEPROM controller also allows the host system to read, write and erase the contents of the Serial

EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for 128 x 8-bit operation.

TABLE 3-8:

32-BIT ENDIAN ORDERING LOGIC OPERATION

Host Data Bus

D[31:24]

D[23:16]

D[15:8]

D[7:0]

END_SEL = 0

3210

END_SEL = 1

TABLE 3-9:

16-BIT ENDIAN ORDERING LOGIC OPERATION

Host Data Bus

D[15:8]

D[7:0]

END_SEL = 0

A1 = 1

A1 = 0

END_SEL = 1

A1 = 1

A1 = 0

END_SEL = 0

A1 = 1

A1 = 0

END_SEL = 1

A1 = 1

A1 = 0

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