LAN89218 datasheet(8/148 Pages) MICROCHIP

8 / 148 page

LAN89218

DS60001255B-page 8

 2008-2015 Microchip Technology Inc.

1.5

Receive and Transmit FIFOs

The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit

between the host interface and the MAC through which all transmitted and received data and status information is

passed. Deep FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks

thus reducing or minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data

paths. In addition, the RX and TX FIFOs are configurable in size, allowing increased flexibility.

1.6

Host Bus Interface (SRAM Interface)

The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for

the LAN89218 Control and Status Registers (CSR’s).

The host bus interface is the primary bus for connection to the embedded host system. This interface models an

asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O

transactions are supported.

The LAN89218 host bus interface supports 32-bit and 16-bit bus transfers. Internally, all data paths are 32-bits wide.

The LAN89218 can be interfaced to either Big-Endian or Little-Endian processors and includes mixed endian support

for FIFO accesses.

1.7

Interrupt Controller

The LAN89218 supports a single programmable interrupt. The programmable nature of this interrupt allows the user

the ability to optimize performance dependent upon the application requirement. Both the polarity and buffer type of

the interrupt pin are configurable for the external interrupt processing. The interrupt line can be configured as an

open-drain output to facilitate the sharing of interrupts with other devices. In addition, a programmable interrupt de-

assertion interval is provided.

1.8

GPIO Interface

A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the LAN89218. It

is accessible through the host bus interface via the CSRs. The GPIO signals can function as inputs, push-pull outputs

and open drain outputs. The GPIO’s (GPO’s are not configurable) can also be configured to trigger interrupts with

programmable polarity.

1.9

Serial EEPROM Interface

A serial EEPROM interface is included in the LAN89218. The serial EEPROM is optional and can be programmed

with the LAN89218 MAC address. The LAN89218 can optionally load the MAC address automatically after power-

on reset, hardware reset, or soft reset.

1.10

Power Management Controls

The LAN89218 supports comprehensive array of power management modes to allow use in power sensitive

applications. Wake on LAN, Link Status Change and Magic Packet detection are supported by the LAN89218. An

external PME (Power Management Event) interrupt is provided to indicate detection of a wakeup event.

1.11

General Purpose Timer

The general-purpose timer has no dedicated function within the LAN89218 and may be programmed to issue a timed

interrupt.

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