LAN89218 datasheet(83/148 Pages) MICROCHIP

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DS60001255B-page 83

LAN89218

5.3.9.1

Allowable Settings for Configurable FIFO Memory Allocation

TX and RX FIFO space is configurable through the CSR - HW_CFG register defined above. The user must select

the FIFO allocation by setting the TX FIFO Size (TX_FIF_SZ) field in the hardware configuration (HW_CFG) register.

The TX_FIF_SZ field selects the total allocation for the TX data path, including the TX Status FIFO size. The TX

Status FIFO size is fixed at 512 Bytes (128 TX Status DWORDs). The TX Status FIFO length is subtracted from the

total TX FIFO size with the remainder being the TX data FIFO Size. Note that TX data FIFO space includes both

commands and payload data.

RX FIFO Size is the remainder of the unallocated FIFO space (16384 bytes – TX FIFO Size). The RX Status FIFO

size is always equal to 1/16 of the RX FIFO Size. The RX Status FIFO length is subtracted from the total RX FIFO

size with the remainder being the RX data FIFO Size.

For example, if TX_FIF_SZ = 6 then:

Total TX FIFO Size = 6144 Bytes (6KB)

TX Status FIFO Size = 512 Bytes (Fixed)

TX Data FIFO Size = 6144 – 512 = 5632 Bytes

RX FIFO Size = 16384 – 6144 = 10240 Bytes (10KB)

RX Status FIFO Size = 10240 / 16 = 640 Bytes (160 RX Status DWORDs)

RX Data FIFO Size = 10240 – 640 = 9600 Bytes

Table 5-3 shows every valid setting for the TX_FIF_SZ field. Note that settings not shown in this table are reserved

and should not be used.

In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2 kbytes of TX, and

128 bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by the host.

As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO. Depending

on the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any

TX data that may be queued in the TX data FIFO.

Conversely, as data is received by the LAN89218, it is moved from the MAC to the RX MIL FIFO, and then into the

RX data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO. If the RX MIL FIFO

fills up and overruns, subsequent RX frames will be lost until room is made in the RX data FIFO. For each frame of

data that is lost, the RX Dropped Frames Counter (RX_DROP) is incremented.

Note:

The RX data FIFO is considered full 4 DWORDs before the length that is specified in the HW_CFG register.

TABLE 5-3:

VALID TX/RX FIFO ALLOCATIONS

TX_FIF_SZ

TX Data FIFO Size

(Bytes)

TX Status FIFO Size

(Bytes)

RX Data FIFO Size

(Bytes)

RX Status FIFO Size

(Bytes)

1536

512

13440

896

2560

512

12480

832

3584

512

11520

768

4608

512

10560

704

5632

512

9600

640

6656

512

8640

576

7680

512

7680

512

8704

512

6720

448

9728

512

5760

384

10752

512

4800

320

11776

512

3840

256

12800

512

2880

192

13824

512

1920

128

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