UCS1002-2 datasheet(102/114 Pages) MICROCHIP

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Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13)

102

SMSC UCS1002

DATASHEET

10.13.5

Custom Stimulus / Response Pair X - Config 4 - 44h, 48h, 4Ch

The contents of this register are retained in Sleep.

Bits 2 - 0 - CS1_SX_RATIO[2:0] - Determines the voltage divider ratio, as shown in Table 10.36, when

the stimulus response is set to connect a voltage divider (i.e., CS1_SX_RX[3:0] = 0110b, 1001b, or

1100b).

10.14 Current Limiting Behavior Configuration Registers

10.14.1

Applied Current Limiting Behavior - 50h

This register stores the values used by the applied current limiting mode (trip or CC) when the custom

settings are not used. The contents of this register are updated automatically when charger emulation

is completed.

The contents of this register are not retained in Sleep. The contents are updated as needed.

Bits 7 - 6 - SEL_VBUS_MIN[1:0] - Define the VBUS_MIN voltage as shown in Table 10.39.

Bits 4 - 2 - SEL_R2_IMIN[2:0] - Define the IBUS_R2MIN current as shown in Table 10.40.

Bits 1 - 0 - RESERVED.

10.14.2

Custom Current Limiting Behavior Configuration - 51h

The Custom Current Limiting Behavior Configuration register allows programming of current limit

parameters. These controls are used when a portable device handshakes using the Legacy charger

emulation profiles (except Legacy 2), the Custom charger emulation profile, or does not handshake as

a dedicated charger (i.e., a power thief).

The contents of this register are retained in Sleep.

Bits 7 - 6 - CS_VBUS_MIN[1:0] - Defines the Custom VBUS_MIN voltage as shown in Table 10.39. Note

that VBUS_MIN is checked even when operating with trip current limiting.

Table 10.38 Current Limit Behavior Configuration Registers

ADDR

R/W

DEFAULT

50h

Applied

Current

Limiting

Behavior

SEL_VBUS_

MIN[1:0]

(VBUS_MIN)

SEL_R2_IMIN[2:0]

(IBUS_R2MIN as shown

in Figure 7.2)

82h

51h

R/W

Custom

Current

Limiting

Behavior

Config

CS_VBUS_MIN

[1:0]

(VBUS_MIN)

CS_R2_IMIN[2:0]

(IBUS_R2MIN as shown

in Figure 7.2)

82h

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