UCS1002-2 datasheet(74/114 Pages) MICROCHIP

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Programmable USB Port Power Controller with Charger Emulation

Datasheet

Revision 1.4 (07-16-13)

SMSC UCS1002

DATASHEET

that the Legacy charger emulation profiles and the BC1.2 DCP charger emulation profile do not use

Stimulus / Response Pair #3.

10.3.2

Interrupt Status - 10h

Bit 7 - ERR - Indicates that an error was detected and the device has entered the Error state. Writing

this bit to a ‘0’ will clear the Error state and allows the device to be returned to the Active state. When

written to ‘0’ all error conditions are checked. If all error conditions have been removed, the UCS1002

returns to the Active state. This bit is set automatically by the UCS1002 when the Error state is entered.

Regardless of the fault handling mechanism used, if any other bit is set in the Interrupt Status register

(10h), the device will not leave the Error state.

This bit is cleared automatically by the UCS1002 if the Auto-recovery fault handling functionality is

active and no error conditions are detected. Likewise, this bit is cleared when the PWR_EN control is

disabled.



‘0’ (default) - There are no errors detected.



‘1’ - One or more errors have been detected, and the UCS1002 has entered the Error state.

APPLICATION NOTE: If the Auto-recovery fault handling is not used, the ERR bit must be written to a logic '0' to

be cleared. It will also be cleared when the PWR_EN control is disabled.

APPLICATION NOTE: Note that the ERR bit does not necessarily reflect the ALERT# pin status. The ALERT# pin

may be cleared or asserted without the ERR bit changing states.

Bit 6 - DISCHARGE_ERR - Indicates that the UCS1002 was unable to discharge the VBUS node. This

bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared. This

bit will cause the ALERT# pin to be asserted and the device to enter the Error state.

Bit 5 - RESET - Indicates that the UCS1002 has just been reset and should be re-programmed. This

bit will be set at power up. This bit is cleared when read or when the PWR_EN control is toggled.The

ALERT# pin is not asserted when this bit is set. This data is retained in the Sleep state.

Bit 4 - MIN_KEEP_OUT - Indicates that the V-I output on the VBUS pins has dropped below VBUS_MIN.

This bit will be cleared when read if the error condition has been removed or if the ERR bit is cleared.

This bit will cause the ALERT# pin to be asserted and the device to enter the Error state.

Bit 3 - TSD - Indicates that the internal temperature has exceeded TTSD threshold and the device has

entered the Error state. This bit will be cleared when read if the error condition has been removed or

if the ERR bit is cleared. This bit will cause the ALERT# pin to be asserted and the device to enter

the Error state.

Table 10.5 EM_STEP Bit Decode

EM_STEP[1:0]

STIMULUS / RESPONSE #

None applied /

Waiting for Current

#3 if applicable

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