UCS1002-2 datasheet(45/114 Pages) MICROCHIP

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Programmable USB Port Power Controller with Charger Emulation

Datasheet

SMSC UCS1002

Revision 1.4 (07-16-13)

DATASHEET

5.3.3

M1, M2, and EM_EN Inputs

The M1, M2, and EM_EN input controls determine the Active mode and affect the power state (see

Table 5.1, "Power States Control Settings" and Table 9.1, "Active Mode Selection"). When these

controls are all set to ‘0’ and PWR_EN is enabled, the UCS1002 Attach and Removal Detection feature

is disabled.In SMBus mode, the M1, M2, and EM_EN pin states will be ignored by the UCS1002 if the

PIN_IGNORE configuration bit is set (see Section 10.4.3); otherwise, the M1_SET, M2_SET, and

EM_EN_SET configuration bits (see Section 10.4.3) are checked along with the pins.

5.3.4

PWR_EN Input

The PWR_EN control enables the port power switch to be turned on if conditions are met and affects

the power state (see Table 5.1, "Power States Control Settings"). The port power switch cannot be

closed if PWR_EN is disabled. However, if PWR_EN is enabled, the port power switch is not

necessarily closed (see Section 5.1.4, "Active State Operation"). Polarity is controlled by the SEL pin.In

SMBus mode, the PWR_EN pin state will be ignored by the UCS1002 if the PIN_IGNORE

configuration bit is set (see Section 10.4.3); otherwise, the PWR_EN_SET configuration bit (see

Section 10.4.3) is checked along with the pin.

5.3.5

Latch Input

The Latch input control determines the behavior of the fault handling mechanism (see Section 7.6,

"Fault Handling Mechanism").

When the UCS1002 is configured to operate in Stand-alone mode (see Section 4.3, "Stand-alone

Operating Mode"), the LATCH control is available exclusively via the LATCH pin (see Section

Table 4.10, "Stand-alone Fault and Attach Detection Selection"). When the UCS1002 is configured to

operate in SMBus mode, the LATCH control is available exclusively via the LATCH_SET configuration

bit (see Section 10.4.3, "Switch Configuration - 17h").

5.3.6

S0 Input

The S0 control enables the Attach and Removal Detection feature and affects the power state (see

Table 5.1, "Power States Control Settings"). When S0 is set to ‘1’, an Attach Detection event must

occur before the port power switch can be turned on. When S0 is set to ‘0’, the Attach and Removal

Detection feature is not enabled.

When the device is configured to operate in SMBus mode, (see Section 4.3, "Stand-alone Operating

Mode"), the S0 control is available exclusively via the S0_SET configuration bit (see Section 10.4.3,

"Switch Configuration - 17h"). Otherwise, the S0 control is available exclusively via the S0 pin since

the SMBus protocol will be disabled.

5.4

Discrete Output Pins

5.4.1

ALERT# and A_DET# Output Pins

The ALERT# pin is an active low open-drain interrupt to the host controller. The ALERT# pin is

asserted (by default - see ALERT_MASK in Section 10.4.1, "General Configuration - 15h") when an

error occurs (see Section 10.3.2, "Interrupt Status - 10h").The ALERT# pin can also be asserted when

the LOW_CUR (portable device is pulling less current and may be finished charging) or TREG (thermal

regulation temperature exceeded) bits are set and linked. As well, when charge rationing is enabled,

the ALERT# pin is asserted by default when the current rationing threshold is reached (as determined

by RATION_BEH[1:0] - see Table 7.1, "Charge Rationing Behavior"). The ALERT# pin is released

when all conditions that may assert the ALERT# pin (such as an error condition, charge rationing, and

TREG and LOW_CHG if linked) have been removed or reset as necessary.

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