SST49LF080A datasheet(18/50 Pages) MICROCHIP

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DS20005086B

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8 Mbit LPC Flash

SST49LF080A

Data Sheet

Chip-Erase Operation

The SST49LF080A devices provide a Chip-Erase operation, which allows the user to erase the entire

memory array to the “1s” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command

sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal

Erase operation begins with the rising edge of the sixth WE#. During the internal Erase operation, the

only valid read is Toggle Bit or Data# Polling. See Table 11 for the command sequence, Figure 25 for

Chip-Erase timing diagram, and Figure 37 for the flowchart. Any commands written during the Chip-

Erase operation will be ignored.

Write Operation Status Detection

The SST49LF080A devices provide two software means to detect the completion of a Write (Program

or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two

status bits: Data# Polling D[7] and Toggle Bit D[6]. The End-of-Write detection mode is enabled after

the rising edge of WE# which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a

Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this

occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with

either D[7] or D[6]. In order to prevent spurious rejection, if an erroneous result occurs, the software

routine should include a loop to read the accessed location an additional two (2) times. If both reads

are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST49LF080A device is in the internal Program operation, any attempt to read DQ7 will pro-

duce the complement of the true data. Once the Program operation is completed, DQ7 will produce

true data. Note that even though DQ7 may have valid data immediately following the completion of an

internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data

bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase

operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed,

DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# pulse for Program

operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth

WE# pulse. See Figure 20 for Data# Polling timing diagram and Figure 35 for a flowchart. Proper sta-

tus will not be given using Data# Polling if the address is in the invalid range.

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