SST49LF080A datasheet(14/50 Pages) MICROCHIP

14 / 50 page

DS20005086B

11/14

8 Mbit LPC Flash

SST49LF080A

Data Sheet

Toggle Bit

During the internal Program or Erase operation, any consecutive attempts to read D[6] will produce

alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is

completed, the toggling will stop.

Multiple Device Selection

Multiple LPC flash devices may be strapped to increase memory densities in a system. The four ID

pins, ID[3:0], allow up to 16 devices to be attached to the same bus by using different ID strapping in a

system. BIOS support, bus loading, or the attaching bridge may limit this number. The boot device

must have an ID of 0 (determined by ID[3:0]); subsequent devices use incremental numbering. Equal

density must be used with multiple devices.

When used as a boot device, ID[3:0] must be strapped as 0000; all subsequent devices should use a

sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). With the hardware strapping, ID informa-

tion is included in every LPC address memory cycle. The ID bits in the address field are inverse of the

hardware strapping. The address bits [A24:A23,A21:A20] are used to select the device with proper IDs.

See Table 7 for IDs. The SST49LF080A will compare these bits with ID[3:0]’s strapping values. If there

is a mismatch, the device will ignore the remainder of the cycle.

Table 7: Multiple Device Selection Configuration

Device #

Hardware Strapping

Address Bits Decoding

ID[3:0]

A24

A23

A21

A20

0 (Boot device)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

T7.0 25026

SST49LF080A датащи(PDF) 14 Page - Microchip Technology

SST49LF080A датащи(HTML) 14 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

датащи скачать

ссылки URL