SST49LF080A datasheet(16/50 Pages) MICROCHIP

16 / 50 page

DS20005086B

11/14

8 Mbit LPC Flash

SST49LF080A

Data Sheet

General Purpose Inputs Register

The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the

SST49LF080A. It is recommended that the GPI[4:0] pins be in the desired state before LFRAME# is

brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle.

There is no default value since this is a pass-through register. See the General Purpose Inputs Regis-

ter table for the GPI_REG bits and function, and Table 9 for memory address locations for its respec-

tive device strapping.

JEDEC ID Registers

The JEDEC ID registers identify the device as SST49LF080A and manufacturer as SST in LPC mode.

See Table 9 for memory address locations for its respective JEDEC ID location.

Table 9: Memory Map Register Addresses for SST49LF080A

Device #

Hardware Strapping ID[3:0]

GPI_REG

JEDEC ID

Manufacturer

Device

0 (Boot device)

0000

FFBC 0100H

FFBC 0000H

FFBC 0001H

0001

FFAC 0100H

FFAC 0000H

FFAC 0001H

0010

FF9C 0100H

FF9C 0000H

FF9C 0001H

0011

FF8C 0100H

FF8C 0000H

FF8C 0001H

0100

FF3C 0100H

FF3C 0000H

FF3C 0001H

0101

FF2C 0100H

FF2C 0000H

FF2C 0001H

0110

FF1C 0100H

FF1C 0000H

FF1C 0001H

0111

FF0C 0100H

FF0C 0000H

FF0C 0001H

1000

FEBC 0100H

FEBC 0000H

FEBC 0001H

1001

FEAC 0100H

FEAC 0000H

FEAC 0001H

1010

FE9C 0100H

FE9C 0000H

FE9C 0001H

1011

FE8C 0100H

FE8C 0000H

FE8C 0001H

1100

FE3C 0100H

FE3C 0000H

FE3C 0001H

1101

FE2C 0100H

FE2C 0000H

FE2C 0001H

1110

FE1C 0100H

FE1C 0000H

FE1C 0001H

1111

FE0C 0100H

FE0C 0000H

FE0C 0001H

T9.0 25026

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