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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32L081CB датащи(PDF) 94 Page - STMicroelectronics |
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STM32L081CB датащи(HTML) 94 Page - STMicroelectronics |
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94 / 110 page  Electrical characteristics STM32L081xx 94/110 DocID027513 Rev 4 I2S characteristics Note: Refer to the I2S section of the product reference manual for more details about the sampling frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral behavior, source clock precision might slightly change them. DCK depends mainly on the ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of (I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition. Table 70. I2S characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S Main clock output - 256 x 8K 256xFs (2) MHz fCK I2S clock frequency Master data: 32 bits - 64xFs MHz Slave data: 32 bits - 64xFs DCK I2S clock frequency duty cycle Slave receiver 30 70 % tv(WS) WS valid time Master mode - 15 ns th(WS) WS hold time Master mode 11 - tsu(WS) WS setup time Slave mode 6 - th(WS) WS hold time Slave mode 2 - tsu(SD_MR) Data input setup time Master receiver 0 - tsu(SD_SR) Slave receiver 6.5 - th(SD_MR) Data input hold time Master receiver 18 - th(SD_SR) Slave receiver 15.5 - tv(SD_ST) Data output valid time Slave transmitter (after enable edge) - 77 tv(SD_MT) Master transmitter (after enable edge) - 8 th(SD_ST) Data output hold time Slave transmitter (after enable edge) 18 - th(SD_MT) Master transmitter (after enable edge) 1.5 - 1. Guaranteed by characterization results. 2. 256xFs maximum value is equal to the maximum clock frequency. |
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